Gold standard for HyperRam memory device for your IP, SoC, and system-level design verification.

HyperRam in production since 2018 for many production designs.

The Cadence® Memory Model Verification IP (VIP) for HyperRam provides verification of the HyperRam controller using the HyperBus as well as xSPI Interface protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperRam is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

Supported specification: Features of Cypress (Infineon) and Winbond. The Cypress (Infineon) HyperRam device supports both interfaces: HyperBus as well as Octal Interface as HyperRam1.0 and HyperRam2.0 respectively.

HyperRam diagram

Product Highlights

  • Dozens of protocol and timing checkers to easily catch design bugs
  • Dozens of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents
  • Ability to check for errors and change error severity
  • Ability to dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Support testbench language interfaces for SystemVerilog and UVM

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Density

  • From 64Mb to 128Mb

Reset

  • Hardware Reset via RESET# pin

Read and Write

  • Write Enable and Write Disable commands to enable WEL latch for xSPI Octal Interface Support - Cypress HyperRAM 2.0
  • Supports Read/Write operation for registers: ID0 and ID1 (Read Only) and CR0/1 (Read/Write)
  • For xSPI Octal Interface Support - Cypress HyperRAM 2.0: Read and Write any register and Read ID Select Burst type from CR1[7] bit

Burst

  • Wrapped burst with lengths of 16, 32, 64, and 128 bytes, Linear burst, hybrid burst: One wrapped burst followed by linear burst.

DCARS

  • DDR Center-Aligned Read Strobe Functionality for Cypress

Extended I/O Support

  • Winbond Specific: DQ[15:0] and RWDS[1:0]

Winbond Specific

  • Hybrid Sleep Mode, Partial Array Refresh, Master Clock Type, and Software Reset

Power Modes and Software Reset

  • For xSPI Octal Interface Support - Cypress HyperRAM 2.0, support of Deep Power Down and Software Reset: Reset and Reset Enable

Simulation Test Suite

MM comes along with a rich testsuite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

Master your tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with Online trainings, VIP Portal, application notes, and troubleshooting articles