The gold standard memory model intended to be compatible with the highly anticipated JEDEC LPDDR6 standard for your IP, Subsystem, SoC, and system-level design verification in high-performance computing and artificial intelligence. First-to-Market, with Multiple Early Adopters of Production Designs, targeting full LPDDR6 support.

This Cadence® Verification IP (VIP) is intended for modeling the upcoming JEDEC® Low-Power Memory Device, LPDDR6 design specification. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for LPDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

Product Highlights

  • Command decoding protocol checkers to easily catch design bugs
  • Transaction callbacks for all commands and device memory events
  • Command's operand functional coverage in SystemVerilog
  • Testbench language interfaces for SystemVerilog and UVM

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

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