Overview

Gold standard for JEDEC® LPDDR4 memory device for your IP, SoC, and system-level design verification.

In production since 2015 on dozens of production designs.

This Cadence® Verification IP (VIP) supports the JEDEC® Low Power Memory Device, LPDDR4 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The LPDDR4 VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

LPDDR4 diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Hundreds of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Ability to optionally skip initializations or dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DFI LPDDR4 solution for IP level verification
  • Plug-and-play connectivity to System Performance Analyzer for Sub-system or SoC performance verification
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Support of passive mode, meaning VIP only monitors, checkers and coverage are enabled

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description
Speed (Mt/s)
  • 2133MHz (4266MT/s)

Device Density
  • Supports a wide range of device densities from 4Gb to 32Gb
Dual Channels
  • Supports two channels that can function independently

General DDR Functionality and Timing Checks
  • Precharge, Activate, Read, Write, Mask Write, Mode Register Read, Mode Register Write, Power Down, Refresh, Self Refresh, RFM and related timing checks
Data Mask and Data Bus Inversion
  • Data on the bus can be inverted during both read and write to save power; both Data Mask and Data Bus inversion features can be set through mode registers
On-the-Fly Burst Length
  • Bust length during Read, Write, and Mask Write can be set on the fly through command data and mode registers
Configurable Preamble and Postamble
  • Allows preamble and postamble to be configured for Read, Write, and Mask Write
Frequency Set Points
  • Allows LPDDR4 to be switched between two differing operating frequencies by duplicating mode register parameters commonly changed with operating frequency
FIFO Register and DQS-DQ Training
  • Supports Read FIFO and Write FIFO commands used during Write training
Multipurpose Command (MPC)
  • Supports all 7 MPC commands

Command Bus Training
  • The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup and hold requirements
Latency Code Frequency Table
  • Supports and checks all read and write latency requirements for a given frequency

VREF Settings
  • Supports CA and DQ voltage reference settings
Single-Ended Mode
  • Supports single-ended mode for Clock and Strobe
Byte Mode
  • Supports byte-mode devices from 2Gb to 32Gb
Tccd+n Reads/Writes
  • Supports all combinations of Reads merging and Writes merging placed Tccd+n apart
Delay Modeling
  • Delay modeling of input and output signals, display of delay modeling internal signals on the simulator waveform
  • Support for delay randomization on tDQSCK with drifts

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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