Simulation VIP for HBM4
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Overview
The gold standard memory model is intended to be compatible with the highly anticipated JEDEC HBM4 standard for your IP, Subsystem, SOC, and system-level design verification. First-to-Market with multiple early adopters of production designs, targeting full HBM4 support.
This Cadence Verification IP (VIP) is intended for modeling the upcoming High-Bandwidth Memory (HBM4) interface design specification standard as planned by JEDEC. It provides a highly capable compliance verification solution applicable to IP, sub-system, system-on-chip (SoC), and system-level verification. The Cadence Memory Model for HBM4 models a single channel of HBM4 DRAM; this model can be replicated for multiple channels and stacks. The Memory Model for HBM4 runs on all leading simulators and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
HBM4 DRAM is the highly anticipated next-generation evolution of the currently published HBM specification planned by JEDEC, aiming for low-power, double-data-rate, high-data-width, volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The HBM4 DRAM memory device will be designed to satisfy the performance and memory density demands of leading-edge high-performance devices.
Supported specifications: The HBM4 memory model follows the HBM4 developing standard.
Product Highlights
- Basic protocol and timing checkers to easily catch design bugs
- Predefined configurations available on ememory.com
- Transaction and memory callbacks for all protocol, model states, and device memory events
- Ability to dynamically change configuration parameters
- Ability to dynamically change the density or speedbin of the device memory
- Packet tracker creation for easy debugging
- Functional coverage in SystemVerilog
- Supports testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
- Supports waveform debugger for easy debugging from waveform viewer
Simulation Test Suite
MM has a rich test suite of scenarios for easy MM evaluation and deployment.
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