Best-in-class DFI Verification IP for your IP, SoC, and system-level design testing.

Complete solution for extensive and fast verification used by multiple production designs.

The Cadence Verification IP (VIP) for DFI provides a mature, highly capable compliance verification solution for the DFI protocol. The VIP supports the simulation platform and enables metric-driven verification of IP and system-on-chip (SoC) designs against DFI protocol specifications. DFI VIP supports both the memory controller (MC) traffic generation and the PHY component, which samples from the DFI interface and drives to the memory interface for different memory variants. The VIP for DFI is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Supported specification: DDR PHY Interface Specification v4.0, v5.0 and v5.1

DFI diagram

Product Highlights

  • Generates constrained-random bus traffic with predefined error injection
  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Ability to skip initializations or dynamically change configuration parameters
  • Dynamic activation support to enable users to set the VIP as active or passive without changing the testbench while determining the instance to instantiate during run time
  • Packet tracker creation for easy debugging
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DRAM Memory Models for complete IP-level verification
  • MM-DFI Auto Config ​- Automatic updates of timing parameters of DFIMC/DFIPHY VIP based on MM configuration
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC

Key Features

The following table describes key features from the specifications for the simulated DFI MC and DFI PHY that are implemented in the VIP:

Feature Name

Description

Supported Memory

DFI MC

Command Interface

  • Drives command on different phases based on memory protocol requirement
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Command-to-Command Delay

  • Configurable different timing constraint requirements while driving a command through DFI interface for the memory
  • DDR4-5, LPDDR4-5, HBM2E-3, HBM4

Data Interface

  • Read and write data interface
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Update Interface

  • MC-initiated and PHY initiated updates
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Training Interface

  • CA, write, write DQ, read training (Both MC-initiated and PHY-initiated)
  • DDR4, LPDDR4

PHY Master Interface

  • Supports PHY master interface
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

WCK Interface

  • Supports WCK interface
  • LPDDR5

Frequency Change Protocol

  • Initiates frequency change
  • DDR4-5, LPDDR4-5, HBM2E-3, HBM4

Low-Power Control

  • Initiates low-power entry as per DFI5.x and DFI4.0
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Data CS Gap

  • Data path chip select gap (per rank delay line support)
  • DDR4-5, LPDDR4-5

Refresh Command

  • Sends refresh all and refresh per bank command on every internal
  • DDR4-5, LPDDR4-5, HBM2E-3, HBM4

DFI Interactions

  • DFI interaction rules as per DFI 5.x
  • DDR5, LPDDR5, HBM3, GDDR6-7, HBM4

2N Mode

  • Command transmission in 2N mode
  • DDR5

DBI and Data Mask

  • Generates inverted/masked write data and invert received read data with dfi_rddata_dbi enabled
  • DDR4-5, LPDDR4-5, HBM2E-3, HBM4

CRC

  • Generates CRC and error injection
  • DDR4-5

Frequency Ratio

  • All possible frequency ratios as per specification
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

GearDown Mode

  • Command transmission in GearDown mode
  • DDR4

Checkers

  • Performs timing and protocol checks for signals driven by PHY
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Multi-Channel Mode

  • Configurable single/multiple (independent/combine) channel interface
  • LPDDR4, HBM2E-3, GDDR6, HBM4

RCK Interface

  • Enable/disable control on RCK signal for read transfer
  • GDDR7

DQE/DQX Interface

  • DQE/DQX Interface for CRC/7-8Bit encoding
  • GDDR7

CABI Interface

  • CABI interface for command inversion
  • GDDR6

Read Data EDC Interface

  • Sampling EDC signals with slice control using enable signal
  • GDDR6

DFI PHY

Command Interface

  • Drives command on different phases based on memory protocol requirement
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Data Interface

  • Read and write data interface
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Update Interface

  • MC-initiated and PHY-initiated updates
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

PHY Master Interface

  • Supports PHY master interface
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

WCK Interface

  • Supports WCK interface
  • LPDDR5

Frequency Change Protocol

  • Initiates frequency change
  • LPDDR4-5, DDR4-5

Low-Power Control

  • Initiates low-power entry as per DFI5.x and DFI4.0
  • DDR4-5, LPDDR4-5, HBM2E-3, GDDR6-7, HBM4

Data CS Gap

  • Data path chip select gap (per rank delay line support)
  • LPDDR4-5, DDR4-5

DFI Interactions

  • DFI interaction rules as per DFI 5.x
  • LPDDR5, DDR4-5, HBM3, HBM4

DBI and Data Mask

  • Generates inverted/masked write data and invert received read data with dfi_rddata_dbi enabled
  • LPDDR4-5, DDR4-5, HBM3, HBM4

Frequency Ratio

  • All possible frequency ratios as per specification
  • LPDDR4-5, DDR4-5, HBM2E-3, GDDR6-7, HBM4

DRAM Interface

  • Supports DRAM interface as per required by DRAM
  • LPDDR4-5, DDR4-5, HBM2E-HBM3, GDDR6-7, HBM4

Initialization/PHY Training

  • Fully configurable Initialization training for memory model, also PHY can initiate training independently through registers
  • LPDDR4-5, DDR4-5, HBM2E-HBM3, GDDR6-7, HBM4

Run-time Configurations

  • PHY decodes MRW/MPC commands and auto-update its configuration, read-write latency based on that
  • LPDDR4-5, DDR4-5, HBM2E-HBM3, GDDR6-7, HBM4

Multi-Rank

  • Supports multi-rank transfer interface
  • LPDDR4-5, DDR4-5

DBI

  • Generates inverted write data and inverted received read data if DBI is enabled in PHY
  • LPDDR4-5

ECC

  • Generates ECC for Write Data and check ECC for received Read Data ECC is enabled in PHY
  • LPDDR5

WCK

  • Supports the generation of WCK based on WCK:CK ratio
  • LPDDR5

CK

  • Supports the generation of DRAM clock based on frequency ratio
  • LPDDR4-5, DDR4-5, HBM2E-3, GDDR6, HBM4

Training

  • Supports all the training required for DRAM
  • LPDDR4-5, DDR4-5, HBM2E-HBM3, GDDR6-7, HBM4

CRC

  • Generation of CRC when PHY CRC Mode is on
  • DDR4-5,

Dual Channel

  • Configurable single/dual (independent/combine) channel interface
  • LPDDR4

CABI Interface

  • CABI interface for command inversion
  • GDDR6

Read Data EDC Interface

  • Driving EDC signals with slice control using enable signal
  • GDDR6

Simulation Test Suite

Extensive test suite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.

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