Gold standard for JEDEC®DDR5 RDIMM memory device for your IP, SoC, and system-level design verification.

First to market with full DDR5 RDIMM support.

This Cadence® Verification IP (VIP) supports the JEDEC® DDR5 SDRAM Registered DIMM Design Specification, the DDR5 RDIMM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 RDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 RDIMM is the next-generation DIMM specification with improvements in the areas of speed, configuration, reliability, and power saving. It supports speeds up to 4800 speed grade.

Supported specification: JEDEC DDR5 SDRAM Rev 1.01, JEDEC DDR5RCD01.

DDR5 RDIMM diagram

Product Highlights

  • Thousands of protocol and timing checkers to easily catch design bugs
  • Multiple predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Ability to optionally skip initializations or dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DFI DDR5 solution for IP level verification
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


DIMM Types



  • 32Gb, 64Gb, and 128Gb


  • 3200, 3600, 4000, 4400, and 4800


  • x4 and x8

DIMM Configuration

  • Supports up to 2 ranks and dual independent channels

DRAM Features

  • Supports all DDR5 SDRAM features as stated in DDR5 MM product page


  • DCSTM, QCSTM, DCATM, CAPTM, BCS Training, BCOM Pass-Through Mode

ECC Checks Bits

  • Optional DRAM instantiation for checks bits

RCD Data Rate

  • Supports DDR, SDR1, and SDR2 modes


  • Optional support for checking even parity; in case of errors: Gate DRAM commands

Control Word

  • Output Delay Control Word for CS, RW04 Control Word, most of the control word definitions are now supported

I2C Interface

  • Supports I2C interface for RCD for both Byte and Block Mode Write and Read Operations

Output Delay Modeling

  • Supports Output Delay Modeling for RCD

Bus Inversion

  • Supports RCD Bus Inversion

Inter Rank Odt

  • Supports Inter Rank Odt Checks

Self Refresh

  • Supports Self Refresh with and without Clock Stop for RCD

Control Word Read and Write

  • Supports front-door access of RCD Control Word Registers, both Read and Write operations can be performed to RCD control word registers

Transparent Mode

  • Supports Transparent mode

Address Mirroring

  • DDR5 SDRAM supports the MIR pin, Host is not required to do anything special for odd Rank for all types of DDR5 DIMMs

Data Buffer Interface

  • Date Buffer interface is supported by DDR5RCD, refer to DDR5 LRDIMM page for more details

Simulation Test Suite

MM comes along with a rich testsuite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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