Simulation VIP for DDR5 MRDIMM
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Overview
The gold standard memory model is intended to be compatible with the highly anticipated JEDEC DDR5 MRDIMM standard for your IP, Subsystem, SoC, and system-level design verification in high-performance computing and artificial intelligence. First-to-market, with multiple early adopters of production designs, targeting full DDR5 MRDIMM support.
This Cadence Verification IP (VIP) is intended for modeling the upcoming DDR5 Multiplexed Rank DIMM Design Specification standard as planned by JEDEC. It is built on top of a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), sub-system, system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 MRDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
DDR5 MRDIMM is the highly anticipated next-generation DIMM specification planned by JEDEC with improvements in data transfer rates and system performance, targeting the high-performance computing and AI application space. It aims to support doubling of the bandwidth to 12.8 Gbps, with support for higher pin speeds. It is planned to be backward compatible with RDIMM, and will enable reuse of DDR5 DIMM components to leverage the existing LRDIMM ecosystem.
Supported specifications: The DDR5 MRDIMM memory model follows the MRDIMM developing standard.
Product Highlights
- Thousands of protocol and timing checkers to easily catch design bugs
- Multiple predefined configurations based on specific memory vendors' part numbers, datasheets, available on ememory.com
- Transaction and memory callbacks for all protocol, model states, and device memory events
- Ability to optionally skip initializations or dynamically change configuration parameters
- Packet tracker creation for easy debugging
- Extensive functional coverage in SystemVerilog
- Integrated with the DFI DDR5 solution for IP-level verification
- Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
Simulation Test Suite
MM has a rich test suite of scenarios for easy MM evaluation and deployment.
Please contact us for further information.
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