Overview

Gold standard for JEDEC® DDR4 LRDIMM memory device for your IP, SoC, and system-level design verification.

First to market with full DDR4 LRDIMM support.

This Cadence® Verification IP (VIP) supports the JEDEC® DDR4 Unbuffered DIMM (UDIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM) design standards. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The DDR4 RDIMM Memory Model VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR4 LRDIMM diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Multiple predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Ability to optionally skip initializations or dynamically change configuration parameters
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DFI DDR4 solution for IP level verification
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

DIMM Types
  • DDR4 UDIMM, RDIMM, LRDIMM, DDR4 3DS, 3DS UDIMM, 3DS RDIMM, and 3DS LRDIMM

LRDIMM Training Modes
  • Fully supports DWL, HWL, MREP, MRD, and MWD Training modes

Initialization and Reset
  • Use Power Up Reset and Reset with Stable Power with all timing and pin validity checks

Weak Driver Support
  • Supports signal strength modeling. Users can use pull up or pull down on the input pins and the model detects the signal strength and function like a real device

New DIMM Configuration Support
  • Raw Cards with CB bits are mapped to the middle of DQ and DQS buses

Configurable DIMM Topology
  • A number of ranks and components with and the overall interconnect between DIMM, RCD, and DRAM are configurable using SOMAs

Flyby Delays
  • Supports Flyby delay to specify wiring delays for UDIMM, RDIMM and LRDIMM. Can be changed on the fly

ECC Checks Bits
  • Optional DRAM instantiation for checks bits

Address Mirroring
  • RDIMM will optionally mirror the address bits as mentioned in specification

DQ Maps
  • Configurable DQ Maps to match one of the options mentioned in the specification

Core RCD Forwarding Logic
  • DRAM MRS command handling, inversion, mirroring, command latency, propagation delay, gating with parity checks, and different CS modes

RCD Control Word Writes
  • MRS7 interface for CWW and most of the control word settings

Parity
  • Supports optionally checking for even parity. CWW and DRAM commands support gating errors
  • Implements different recovery mechanisms defined in the specification

CA Training
  • Supports Clk to CA and ODT, CKE, CSBAR loop-back modes

DB Control Word Writes
  • MRS7 interface for Buffer Control Word Writes and most of the control word settings

DB Data Latching and Forwarding
  • Latching of Read and Write data to forward it to Host, or the DRAM side depending on the command

DDR4 DB Delay Registers
  • Supports all the Nibble and bit-lane delay registers mentioned in the specification

DB Command Sequence and Parity
  • Supports the command sequence and Parity error along with the relevant buffer Control Words

LRDIMM Rank to Rank Timing Checks
  • Supports timing check for Read and Write accesses to different Ranks

DRAM Features
  • Supports all DDR4 SDRAM features

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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