Overview
Best-in-class Ethernet Verification IP for your IP, SoC, and system-level design testing.
The Cadence Verification IP (VIP) for Ethernet Time-Sensitive Networks (TSN) provides a mature, highly capable compliance verification solution for the TSN protocol stack incorporating bus functional model (BFM) and integrated protocol checkers and coverage. The VIP for Ethernet TSN is designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, helping to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet TSN is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
IEEE P802.1AS-2011 |
|
IEEE 1588-2002 v1 |
|
IEEE 1588-2008 v2 |
|
Credit-Based Shaping |
|
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