Overview

Best-in-class Ethernet Verification IP for your IP, SoC, and system-level design testing.

Incorporating the latest protocol updates, the mature and comprehensive Cadence Verification IP (VIP) for the Ethernet Base-T1 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, the VIP for Base-T1 Ethernet helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Base-T1 Ethernet runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Ethernet Base-T1 diagram

Product Highlights

  • Supports testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Predefined protocol checkers to evaluate the compliance of the DUT model with protocol requirements
  • Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
  • Packet tracker creation for easy debugging
  • Extensive SystemVerilog coverage model with infrastructure for extension

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

10 Base-T1s Interface

Based on IEEE 802.3cg-2019 (Clause 147)

  • 4b/5b Encoder/Decoder
  • 17-bit self-synchronizing scrambler/descrambler
  • PCS Transmit FSM
  • PCS Receive FSM
  • Differential Manchester Encoding (DME) at PMA
  • Supports DME bypass
  • Supports PLCA RS sub-layer (IEEE802.3cg-2019 CL-148)
  • Supports Half-Duplex, Full-Duplex, and Multidrop mode

 

100 Base-T1 Interface

Based on IEEE 802.3bw-2015

  • MII
  • 4b/3b Encoding/Decoding
  • Data Scrambler
  • Side-Stream Scrambler
  • PHY Control
  • Link Monitor

1000 Base-T1 Interface

Based on IEEE 802.3bp-2016

  • GMII
  • 80b/81b Encoding/Decoding
  • Side-Stream Scrambler
  • RS-FEC (450, 406)
  • EEE
  • OAM
  • CL-98 AN
  • PHY Control
  • Link Sync
  • Link Monitor
2.5G Base-T1 Interface

Based on IEEE 802.3ch-2020

  • 64b/65b Encoding/Decoding
  • PCS scrambler/descrambler
  • PCS TX/RX FSM
  • Gray Coding and Precoding
  • RFER Monitor
  • RS-FEC (360, 326)
  • PMA PHY Control
  • PMA Link Sync
  • PMA Link Monitor

Dynamic Switching
  • Run-time speed switching on-the-fly

PMA Bus-Width
  • Configurable PMA bus width: 2 bits for 10M/100M/1000M/2.5G BaseT1

Clock, Jitter, Drift
  • Internal and external clock mode

Flow Control
  • Pause FC and PFC pause FC

Frame Types
  • Ethernet IEEE 802.3 (Type and Length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Pause frame
  • PFC Pause frame
  • Management frame
  • Tagged Frames: Single Tagged (Q-VLAN tag) and Double tagged (S-VLAN tag and Q-VLAN tag)
  • Upper Layer Frames: TCP, UDP, IPV4, IPV6, SNAP, MPLS, FC, MACSEC

Custom Frame
  • Proprietary header support

MDIO Interface
  • MDIO interface as per Clause-22 and Clause-45

Simulation Test Suite

VIP comes with a test suite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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