Overview
Best-in-class Arm SWD Verification IP (VIP) for your IP, SoC, and System-level Design Testing
The Cadence Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol, which is part of the Arm® Debug Interface Specification. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms incorporating the latest protocol updates with integrated automatic protocol checks and a coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SWD runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: SWD v1 and v2 as per Arm Debug Interface specification v6.0 (ADIv6.0).

Product Highlights
Key Features
The following table shows key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Serial Wire Debug Port |
|
Serial Wire/JTAG Debug Port |
|
Error Injection |
|
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