Overview

Best-in-class Arm® AMBA® AXI4-Stream Verification IP (VIP) for your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI4-Stream specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence VIP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for AXI4-Stream helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides a solution for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: AMBA® AXI4-Stream v1.0. AXI5-Steam

AMBA Stream diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Packet tracker creation for easy debugging

Key Features

The following table describes the key features from the specifications that are implemented in the VIP:

Feature Name

Description

Data and address widths
  • Customizable address width up to 32 bits and data width up to 20,000

UserBusSize
  • Increased support for user width

Interface Order Control
  • The user can fully control the order in the interface

Delay control
  • Set the delay between the items on the interface

Manager packet signal control
  • Control the values of the Manager packet signals in the interface

Manager transfer signal control
  • Control the values of the signals in the write data channel

Multiple agent support
  • Support for any number of agents

Simulation Test Suite

VIP comes with a test suite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

Learn More

Related Products

System VIP
Design IP
Xcelium Logic Simulation
Palladium Emulation