Overview

Best-in-class Arm® AMBA® LPI Verification IP (VIP) for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the LPI specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for LPI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides Interconnect Validator connection for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for LPI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: Arm® Q-Channel and P-Channel Interfaces of Low Power Interface Specification

AMBA LPI diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Comprehensive checking model
  • Callbacks access for transaction modification, scoreboarding, and debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive System Verilog coverage

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Agent Type
  • Power Controller or Device

P-Channel
  • Supports P-Channel functionality

Q-Channel
  • Supports Q-Channel functionality

Delay Control
  • Comprehensive control of timing aspects

Reset Release
  • Release of Q-Channel device from reset either with QREQn set to LOW or HIGH

Controllability
  • Both QACTIVE and PACTIVE can be independently controlled through register writes

QACTIVE Bypass
  • Bypassing of QACTIVE is possible when not required

PACTIVE Width Configuration
  • Configurable PACTIVE signal width

Configurable Initial Values
  • Initial QACTIVE and PACTIVE value can be configured to either HIGH or LOW

Waveform Debugger
  • All the channel states are visible through Waveform Debugger

Simulation Test Suite

VIP comes with a test suite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

Learn More

Related Products

System VIP
Design IP
Xcelium Logic Simulation
Palladium Emulation