Overview

Best-in-class Arm® AMBA® Distributed Translation Interface (DTI) Protocol Verification IP (VIP) for your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the Distributed Translation Interface (DTI) specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for DTI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system levels, the VIP for DTI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides a solution for interconnect verification that verifies the correctness and completeness of data. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA® DTI r0p0 Edition 3. AMBA DTI Issue F Update.

AMBA DTI diagram

Product Highlights

  • Supports seamless integration in SystemVerilog, UVM, OVM, e, and SystemC® verification environments
  • Generates constrained-random bus traffic with predefined error injection
  • Comprehensive checking model
  • Could be used as a standalone or with AXI-Stream as transport layer
  • Callbacks access for transaction modification, scoreboarding, and debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive System Verilog coverage

Key Features

The following table shows key features from the specifications that are implemented in the VIP:

Feature Name

Description

Connect and Disconnect Message Group
  • The connection and disconnection of the DTI-TBU and DTI-ATS protocol channel

Translation Request Message Group
  • The DTI-TBU/DTI-ATS translation requests messages to enable the TBU/ATS to find the translation for a given transaction or prefetch a translation

Invalidation and Synchronization Message Group
  • Invalidation operations for the TCU to indicate to the TBU/ATS that certain information must no longer be cached

Register Access Message Group (TBU)
  • The DTI TBU provides implementation defined registers, which can be accessed using these messages

Page request message group (ATS)
  • A PCIe RPs to directly request software makes pages available

DTI-TBU Caching Module
  • The TBU implements a cache model in which translation response information is cached depending upon its intended function

Bypass Translation Mode Support
  • No translation happens via the TCU DTI VIP. The physical address will be the same as the virtual address, and default attributes configured are used

Page Table Walk Support
  • TCU does a Page Table walk to determine the physical address. User can load the page table entries through back door write
Random Mode Support
  • Translation request will be responded with random data in response

Simulation Test Suite

VIP comes with a test suite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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