Best-in-class Arm® AMBA® CHI Verification IP (VIP) for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface (CHI) specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CHI provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms. Cadence provides an integrated solution for interconnect verification, which supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP runs on all major simulators and supports SystemVerilog and e verification languages, along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: AMBA 5 CHI A, B, C, D, E, and F.

AMBA CHI diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Includes embedded memory model in SN models
  • Includes embedded cache model in RN-F models
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Transaction type

  • Monitoring and driving of all protocol Opcodes

Dummy interconnect

  • Dummy CHI-based interconnect support. When interconnect is not present, the Active Hn-F can generate snoop requests and respond to Rn-F commands

Communication layers

  • Liink, network and protocol layer communication

Interface

  • Rn-F, Rn-D, Rn-I to Hn-F, Hn-D, Hn-I, Mn and Hn-F, Hn-I, Mn to Sn-F, Sn-I

Flow control

  • Flow control mechanisms support available across all RnX-to-HnX and HnX-to-SnX links

Channel delay

  • User can control timing of individual flits

Cache model

  • Facilitates the role of actual L2 cache used in a CHI Rn-F

Cache access

  • Supports cache backdoor access as specific or random values can be sent to the cache at the beginning of a test or during run time

CHI-B

  • Monitoring and driving of atomic transactions
  • Monitoring and driving of stashing transactions
  • Support for Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT)
  • Monitoring and driving of de-allocating transactions
  • Optional addition of Data Check and Poison
  • System Coherency Interface, used to connect and disconnect from a coherency domain

CHI-C

  • Monitoring and driving of separate read data and home response
  • Monitoring and driving of combined CompAck and Write Data

CHI-D

  • Supports monitoring and driving of persistent CMO with two-part response
  • Support for Memory Partitioning and Monitoring (MPAM) feature

CHI-E

  • Memory Tagging

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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