Best-in-class Arm® AMBA® AXI Verification IP (VIP) for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for AXI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC and performance analysis that provides automated generation of testbenches. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: AMBA 3 AXI, AMBA 4 AXI, AMBA 4 AXI-Lite, AMBA 5 AXI, and AMBA 5 AXI-Lite interfaces, AMBA AXI issues F, G, and H.

AMBA AXI diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Multiple Agents

  • Supports any number of agents

Data and Address Widths

  • All legal data and address widths

Additional Signaling

  • AxQOS, AxREGION, and user-defined signals introduced in AMBA4 AXI

AXI-Lite

  • AXI-Lite configuration, automatically modifies the agent's behavior accordingly

Automatic Subordinate Responses

  • Support to use automatic Subordinate responses

Transmission Order Control

  • Controls the order of transmission of write transfers (AMBA 3 AXI only), read transfers, and write responses

Data Before Address

  • Sending of data before address transactions when legal

Delay Control

  • Control the delay between the items on the channels

Exclusive Access

  • Monitoring and driving of all exclusive transactions

Locked Transactions

  • Monitoring and driving of locked transactions (AMBA 3 AXI only)

Manager Signal Control

  • Control the values of the burst signals in the read and write address channel and transfer signals in the write data channel

Subordinate Response Control

  • Control over the values of the signals in the read data channel

Transaction Types

  • Monitoring and driving of all read and write transactions

Atomic Transactions

  • Atomic transactions in AMBA 5 AXI

Other Signaling

  • User Loopback Signaling, QoS Accept Signaling and Wake-Up Signaling

Trace Signals

  • Applicable to AXI5 and AXI5-Lite

Untranslated Transactions

  • Support for Untranslated Transactions

Non-Secure Access Identifiers

  • Support for Non-Secure Access Identifiers

MPAM

  • Memory Partitioning and Monitoring functionality

MTE

  • Memory Tagging Extensions functionality

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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