Overview

Best-in-class Arm® AMBA® APB Verification IP (VIP) for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the Advanced Peripheral Bus (APB) specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for APB provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for APB helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides a solution for interconnect verification that verifies the correctness and completeness of data. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specifications: AMBA 2 APB, AMBA 3 APB, AMBA 4 APB, AMBA 5 APB issue D and E.

AMBA APB diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD)

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Data and Address Widths
  • All legal data and address widths

Automatic Completer Responses
  • Support to use automatic Completer responses

Delay Control
  • Control the delay between the items on the channels

Multiple Agents
  • Supports any number of agents

Requester Transfer Signal Control
  • Control the values of the signals in the write data channel

Completer Response Control
  • Control over the values of the signals in the read data channel

Completer Memory Emulation
  • Data consistency check for Completers using memories

Transaction Types
  • Monitoring and driving of all read and write transactions

PPROT and PSTRB
  • Strobe and Protection Type signals as defined in APB4 spec v2.0

Completer Responses
  • PLSVERR signal as defined in APB4 spec v2.0 and in APB3

Completer Response Wait State
  • Completer Response Wait State as defined in APB4 spec v2.0 and in APB3

Support for Parity
  • Parity support for each signal

APB5 Issue D
  • User Signaling, Wakeup Support

APB5 Issue E
  • Root Realm Management, SubSysId support

Simulation Test Suite

VIP comes with a test suite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

Learn More

Related Products

System VIP
Design IP
Xcelium Logic Simulation
Palladium Emulation