Overview
Formally Verify Your Design's Compliance to Popular Protocols
Optimized for high-performance execution and rapid debug, Cadence® Formal Verification IP (VIP) consists of libraries of assertion-based VIP for exhaustively verifying the compliance of a design under test (DUT) to a given protocol. With our Formal VIP, you can find critical bugs early on and shorten your overall verification schedule. All of our Formal VIP are optimized for high-performance execution in our formal engines and Jasper™ ProofGrid™ Intelligent Resource Manager, along with rapid debug with our unique Jasper QuietTrace™ debugging capability. The various VIP also work with our unique Jasper Visualize™ Interactive Debug Environment for early integration of your implementation and the kit and/or rapid protocol customization/extension. The Formal VIP includes reusable “recipes” to explore protocol functionality and intent based on interface events. The protocol-related properties, generated to support early exploration and verification of protocol specifications, are optimized for formal and plug seamlessly into the simulation environment.

Key Benefits
Formal VIP Key Benefits
Exhaustively Verify Compliance
Verifies compliance to standard protocols with exhaustive assertion-based verification IP libraries
Plug and Play
Enables automated, encapsulated, plug-and-play capabilities
Increase Design Quality
Provides quality support for spec-compliant designs
Optimized for Formal
Optimized for Jasper Formal Verification Platform
Supports Leading Simulators
Also compatible with the leading simulators including Xcelium™ Logic Simulation