Speeding Verification on Hardware-Based Verification
Accelerated Verification IPs (AVIPs) bring an entirely new level of performance to verification through integration with hardware-based verification using Cadence® Palladium® emulation or Cadence Protium prototyping. AVIPs are primarily used to funnel data from a user supplied test bench (TB) to the user's design under test (DUT) and return results from the DUT to the testbench. Additionally, select AVIPs are available for embedded use without a testbench. Cadence AVIPs are available for most standardized protocols with new protocol support launched on a regular basis. Further Cadence AVIPs support or are integrated into a variety of Cadence verification products.
Large SoCs comprised of hundreds of millions to billions of logic gates are becoming the standard for new designs. These designs will bog down software simulators, even when running on the fastest servers with extensive use of parallelism. Further, the necessity of software-driven full chip system-level verification is becoming more critical as software becomes a differentiating factor. The standard solution of using dedicated hardware such as Cadence Palladium emulators and Cadence Protium FPGA-based prototypes can greatly improve simulation performance but generally does not support all the functionality found in Verification IPs, System Verification IPs, and Jasper Formal Verification. Cadence Accelerated Verification IPs address this by bridging the gap between the hardware requirement for synthesizability and the expressiveness of simulation and formal-based verification IPs. AVIPs link a synthesizable bus functional protocol engine that is guaranteed compatible with Cadence hardware verification solutions with a selection of high-level interfaces designed to support software co-verification and test bench creation in the user’s choice of verification language and flow. Advanced features of Verification IPs, System Verification IPs, and Formal Verification such as monitor functions that collect coverage and setting callbacks are not included in the AVIPs but are fully compatible when purchased together.
Accelerated VIP Key Benefits
Hardware-assisted verification enabled by AVIPs can be 10s to 1,000s of times faster than simulation-based verification
Plug and Play
Fully standardized BFM protocols work out of the box with compliant interfaces
Interoperable with Cadence Verification Tools
Palladium and Protium systems, and Xcelium simulation, and Jasper formal software
Accelerated VIP Protocols
- The Cadence AVIP for CAN/CAN-FD provides support for the CAN and CAN-FD protocols.
- The Cadence AVIP for Flexray provides support for the Flexray protocol
- The Cadence AVIP for LIN provides support for the LIN Protocol
Arm AMBA Family Protocols
The Cadence AVIP for AHB provides support for the Arm AMBA 2, AMBA 3, and AMBA 5 AHB Interface Protocol Specifications, including the AHB-Lite subset, as well as the AMBA 2, AMBA 3, and AMBA 4 APB Interface Protocol Specifications, as well as Arm AMBA ACE, ACE-Lite, ACE5, ACE5-Lite, AXI3, AXI4, AXI4-Lite, AXI5, and CHI Interface Protocol Specifications.
- The Cadence AVIP for DisplayPort 2.0 provides support for DisplayPort 1.0 and 2.0 specifications.
- The Cadence AVIP for DSI provides support for the MIPI Display Serial Interface 1.2 and 2.0 specifications.
- The Cadence AVIP for HDMI 2.0 provides support for the HDMI 1.3, 1.4, and 2.0 specifications.
Ethernet Multi-Speed Protocols
The Cadence AVIP for Ethernet Multi-Speed provides support for the IEEE 802.3 standard, including MAC and PCS interfaces at 10M/100M/1G/2.5G/5G/10G/25G/40G/50G/100G/200G/400G/800G speeds.
High Performance Computing and Hyperscale Protocols
- The Cadence AVIP for CCIX provides support for the CCIX protocol
- The Cadence AVIP for Compute Express Link provides support for the CXL 1.0 and 2.0 specifications
- The Cadence AVIP for SR-IOV provides support for the SR-IOV protocol
Mobile Device Protocols
- The Cadence AVIP for Bluetooth Low Energy provides support for the Bluetooth Alliance Specification for Bluetooth Low Energy
- The Cadence AVIP for CSI-2 provides support for the MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2sm) Version 2.0 7 December 2016
- The Cadence AVIP for I2C provides support for the I2C-bus specification and user manual, Rev. 03 19 June 2007
- The Cadence AVIP for I3C provides support for the I3C-bus specification and user manual
- The Cadence AVIP for I2S provides support for the I2S bus specification, Philips Semiconductors - 5 June 1996
- The Cadence AVIP for JESD204 provides support for the JEDEC JESD204 protocol standard
- The Cadence AVIP for Keypad is based on the KEYPAD BFM Requirement Specification, Version 0.4 19 July 2012.
- The Cadence AVIP for MIPI DSI provides support for the MIPI Alliance Specification for C-PHYsm, Version 1.2, MIPI Alliance, Inc. 26 November 2016, MIPI Alliance Specification for Display Serial Interface 2 (DSI-2), Version 1.1 02 May 2018, and MIPI Alliance Specification for D-PHYsm, Version 2.0, MIPI Alliance, Inc.
The Cadence AVIP for PCI Express 6.0 provides support for the PCI Express 6.0 Specification including support for PCI Express versions 2.0, 3.0, 4.0, 5.0, and 6.0.
- The Cadence AVIP for USB 3.1 provides support for the USB 3.0 specification and USB 3.2 Specification including support for USB versions 2.0, 3.0, 3.1, and 3.2 Gen 1
- The Cadence AVIP for USB 4.0 provides support for the USB 4.0 specification
The Cadence AVIP for SATA 1.5/3/6G provides support for the Serial ATA Specification 3.0 and the ATA Command Set specification ATA8 version. Supports both external test bench and embedded operation modes.