Introduction
The System Traffic Libraries provide out-of-the-box scenarios to verify common SoC integration verification domains. The integration challenges involve mixing scenarios that cross multiple functional features (power, coherency, DVM, I/O, PCI Express® (PCIe®), etc'.) that are hard to achieve using manual schemes. The System Traffic Libraries scenarios are written in PSS (Portable Test and Stimulus Standard), which make them applicable for both pre-silicon verification and post-silicon validation and can be executed on simulation, emulation, rapid prototyping (FPGA), and silicon platforms. It is also integrated with Cadence® Verification IP (VIP) for the execution of these scenarios on pre-silicon simulation and emulation platforms.
The System Traffic Libraries are supported for multiple architectures like Arm® v8/v9 and
RISC-V.
The following System Traffic Libraries are available today:
- Coherency Library
- PCIe Integration Library
- Performance Library
Usage Flow
The System Traffic Libraries come with a user-editable configuration sheet to capture key system information that would be used to configure the library scenarios. The System Traffic Libraries scenarios can be extended further or mixed with user code for creating custom scenarios.
The System Traffic Libraries can be generated as C/C++ code and run through the CPU in the design for "embedded flow" or in "coreless" flow in which the protocol-related traffic goes through VIP or AVIP in simulation or emulation.
Coherency System Traffic Library
Addressing system coherency testing
The main features of the Coherency System Traffic Library include:
- Out-of-the box verification plan and test suite for heterogeneous multi core cache-coherent processors
- Visualize scenarios and analyze coverage before test execution
- Support for Arm v8/v9 and RISC-V architectures
PCIe Integration System Traffic Library
Addressing PCIe SoC integration challenges
The main features of the PCIe Integration System Traffic Library include:
- Out-of-the box verification plan and test suite for I/O-coherent PCIe Root port and End point
- Visualize scenarios and analyze coverage before test execution
- Includes tests for Memory, ATS , Deadlocks, power down, registers access and more
Performance System Traffic Library
Analyzing system performance by using traffic profiles and benchmark scenarios
The main features of Performance System Traffic Library include:
- Out-of-the box test suite for industry benchmarks and synthetic traffic profile tests
- Visualize scenarios and analyze coverage before test execution
- Post-processing to analyze performance results
- Work in conjunction with the System Traffic Generator
Test plans are provided for:
- Lmbench (Memory Read/Write/Copy)
- Dhrystone (Simple integer arithmetic, character/single/array operation, pointer/memory access)
- Coremark (matrix manipulation statemachine, cRC)
- Gzip (compress/uncomplex algorithms)
- Synthetic adaptive traffic profiles (ATP) for min latency and max bandwidth scenarios
For further details, please contact our Cadence System Traffic Libraries experts.