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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
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          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre FX Simulator
          • Virtuoso Layout Suite
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          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
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          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
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System Traffic Libraries | Cadence


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Introduction

The System Traffic Libraries provide out-of-the-box scenarios to verify common SoC integration verification domains. The integration challenges involve mixing scenarios that cross multiple functional features (power, coherency, DVM, I/O, PCI Express® (PCIe®), etc'.) that are hard to achieve using manual schemes. The System Traffic Libraries scenarios are written in PSS (Portable Test and Stimulus Standard), which make them applicable for both pre-silicon verification and post-silicon validation and can be executed on simulation, emulation, rapid prototyping (FPGA), and silicon platforms. It is also integrated with Cadence® Verification IP (VIP) for the execution of these scenarios on pre-silicon simulation and emulation platforms.

The System Traffic Libraries are supported for multiple architectures like Arm® v8/v9 and

RISC-V.

The following System Traffic Libraries are available today:

  1. Coherency Library 
  2. PCIe Integration Library
  3. Performance Library

Usage Flow 

The System Traffic Libraries come with a user-editable configuration sheet to capture key system information that would be used to configure the library scenarios. The System Traffic Libraries scenarios can be extended further or mixed with user code for creating custom scenarios.

The System Traffic Libraries can be generated as C/C++ code and run through the CPU in the design for "embedded flow" or in "coreless" flow in which the protocol-related traffic goes through VIP or AVIP in simulation or emulation. 

15193_System_Traffic_Libraries_1

Coherency System Traffic Library

Addressing system coherency testing

15193_System_Traffic_Libraries_2

The main features of the Coherency System Traffic Library include:

  • Out-of-the box verification plan and test suite for heterogeneous multi core cache-coherent processors
  • Visualize scenarios and analyze coverage before test execution
  • Support for Arm v8/v9 and RISC-V architectures

 

PCIe Integration System Traffic Library

Addressing PCIe SoC integration challenges

15193_System_Traffic_Libraries_3

 

The main features of the PCIe Integration System Traffic Library include: 

  • Out-of-the box verification plan and test suite for I/O-coherent PCIe Root port and End point
  • Visualize scenarios and analyze coverage before test execution
  • Includes tests for Memory, ATS , Deadlocks, power down, registers access and more

 

Performance System Traffic Library

Analyzing system performance by using traffic profiles and benchmark scenarios

The main features of Performance System Traffic Library include:

  • Out-of-the box  test suite for industry benchmarks and synthetic traffic profile tests
  • Visualize scenarios and analyze coverage before test execution
  • Post-processing to analyze performance results
  • Work in conjunction with the System Traffic Generator

Test plans are provided for:

  • Lmbench (Memory Read/Write/Copy)
  • Dhrystone (Simple integer arithmetic, character/single/array operation, pointer/memory access)
  • Coremark (matrix manipulation statemachine, cRC)
  • Gzip (compress/uncomplex algorithms)
  • Synthetic adaptive traffic profiles (ATP) for min latency and max bandwidth scenarios

For further details, please contact our Cadence System Traffic Libraries experts. 

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