The System Testbench Generator allows users to describe their testbench topology through IPXact or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation.
- For exhaustive functional verification, the System Testbench Generator generates fully functioning UVM SystemVerilog environments that come complete with Verification IP, scoreboard, clock and reset generation logic, test sequences, routing model with system memory map, and more.
- For subsystem and system integration verification, the System Testbench Generator generates C-based verification environments that can run in simulation or in Cadence® Palladium® and Protium™ hardware platforms.
- Generation of fully functioning UVM SystemVerilog verification environments from user-supplied meta-data for simulation flow
- Generation of C-based verification environments from user-supplied meta-data for simulation, acceleration, and emulation flows
- Support of functional verification and performance analysis
- Fully compatible with Cadence Perspec™ System Verifier for creation of portable stimulus
- Per user configuration, generated environments include Simulation Verification IP (VIP), Acceleration Verification IP (AVIP), system-level scoreboard, routing model with system memory map information, pre-generated ready-to-use tests, and more
For further details, please contact our Cadence System Testbench Generator experts.