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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
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        • 5G Systems and Subsystems
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        • Automotive
        • Hyperscale Computing
      • Technologies
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • Support Process
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System VIP

SoC verification automation enabling up to 10X gain in efficiency

WATCH VIDEO ​Addressing System Level Coherency
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Improve SoC-Level Verification Efficiency by Up to 10X

Smart Verification Technology and Solutions

Nick Heaton gives an introduction to System VIP

  • Related Products

    • Palladium Z1 Enterprise Emulation Platform
    • Protium X1 Enterprise Prototyping Platform
    • Protium S1 Desktop Prototyping Platform
    • Xcelium Logic Simulation
    • Verification IP (VIP) Catalog
    • Perspec System Verifier
    • Accelerated VIP
  • System VIP

    • System Testbench Generator | Cadence
    • System Traffic Libraries | Cadence
    • System Performance Analyzer
    • System Verification Scoreboard | Cadence

Key Benefits

  • Up to 10X gain in chip-level verification efficiency
  • Automatically generates chip-level testbenches for complex Arm, x86, and RISC-V based SoCs
  • Jump-starts SoC testing with rich libraries of tests for SoC coherency, performance bottleneck identification and more
  • Automated SoC level analysis, checking and reporting
  • Full DRAM verification solution accelerates IP-to-SoC-level verification for complex memory controllers, PHYs, and devices for LPDDR5x, DDR5, HMB3, and GDDR6 protocols
  • Portable across simulation, emulation, and prototyping verification engines

As SoC design complexity continues to increase, verification of the fully assembled chip with all its IP components, buses, and interfaces has become the critical path to tape out. Chip-level testbench creation, bus traffic generation, bus performance bottleneck identification, and data and cache coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Missed performance bottlenecks can expose architectural-level oversights late in the project and covering all corner cases for cache coherency across multiple parallel compute engines can take months.

Cadence® System-Level Verification IP (System VIP) takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. It consists of a suite of tools and libraries, each working seamlessly with Cadence’s simulation, emulation, and prototyping engines.

15191_System-Level_VIP_diagram

Cadence System VIP includes:

  • System Testbench Generator allows users to describe their testbench topology through IP-XACT or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation. 
  • System Traffic Library provides users with rich portable stimulus tests for common SoC domains including coherency, performance, PCIe, and NVMe subsystems, which run seamlessly in simulation, emulation, and final silicon. These libraries are integrated with Cadence VIP and Accelerated VIP (AVIP) for fast bring-up.
  • System Performance Analyzer offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals.  
  • System Verification Scoreboard provides data and cache-coherency checkers, which allow users to check data consistency across the system, supporting both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals, and is integrated with Cadence VIP and AVIP.

Using System VIP, Cadence customers creating hyperscale, automotive, mobile, and consumer SoCs can automate chip-level verification and improve efficiency by ten times over existing homegrown methodologies.

System VIP
  • Contact Us
News ReleasesVIEW ALL
  • Cadence Collaborates with Arm to Accelerate Hyperscale Computing and 5G Communications SoC Development 04/27/2021

  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution 10/13/2020

Blogs VIEW ALL
Customers

“We’ve reduced some of the complex SoC verification challenges, especially around IO peripherals. By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”

Tran Nguyen, director of Design Services at Arm.

Resource Library

Video (7)

  • Cadence Delivers Verification Throughput
  • CadenceTECHTALK: Accelerating Performance SoC Testing with Cadence System VIP
  • Better PPA for SoCs with Interconnect Workbench and CoreLink System IP
  • Accelerating SoC Verification Throughput with System VIP
  • Improve SoC-Level Verification Efficiency by Up to 10X with System VIP
  • Smart Verification Technology and Solutions
  • Introduction to System VIP

White Paper (2)

  • Addressing the Challenge of Verifying System-Level Performance
  • System-Level Coherency Verification Challenges

Webinar (1)

  • CadenceTECHTALK: Accelerating Performance SoC Testing with Cadence System VIP

Press Releases (2)

  • Cadence Collaborates with Arm to Accelerate Hyperscale Computing and 5G Communications SoC Development | Cadence
  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution | Cadence

Customers Success (1)

  • Renesas and Cadence
VIEW ALL

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