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CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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IP

An open IP platform for you to customize your app-driven SoC design.

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  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
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AI / Machine Learning

AI IP Portfolio

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See how our customers create innovative products with Cadence Explore Now

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View all Products
  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
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        • AI / Machine Learning
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        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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      • SUPPORT
        • Support Process
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        • Technical Forums
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System VIP

SoC verification automation enabling up to 10X gain in efficiency

WATCH VIDEO ​Addressing System Level Coherency
  • Overview
  • Resources
  • Videos
  • News and Blogs
  • Customers

Improve SoC-Level Verification Efficiency by Up to 10X

Smart Verification Technology and Solutions

Nick Heaton gives an introduction to System VIP

  • Related Products

    • Palladium Z1 Enterprise Emulation Platform
    • Protium X1 Enterprise Prototyping Platform
    • Protium S1 Desktop Prototyping Platform
    • Xcelium Logic Simulation
    • Verification IP (VIP) Catalog
    • Perspec System Verifier
    • Accelerated VIP
  • System VIP

    • System Testbench Generator
    • System Traffic Libraries
    • System Performance Analyzer
    • System Verification Scoreboard

Key Benefits

  • Up to 10X gain in chip-level verification efficiency
  • Automatically generates chip-level testbenches for complex Arm, x86, and RISC-V based SoCs
  • Jump-starts SoC testing with rich libraries of tests for SoC coherency, performance bottleneck identification and more
  • Automated SoC level analysis, checking and reporting
  • Portable across simulation, emulation, and prototyping verification engines

As SoC design complexity continues to increase, verification of the fully assembled chip with all its IP components, buses, and interfaces has become the critical path to tape out. Chip-level testbench creation, bus traffic generation, bus performance bottleneck identification, and data and cache coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Missed performance bottlenecks can expose architectural-level oversights late in the project and covering all corner cases for cache coherency across multiple parallel compute engines can take months.

Cadence® System-Level Verification IP (System VIP) takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. It consists of a suite of tools and libraries, each working seamlessly with Cadence’s simulation, emulation, and prototyping engines.

Cadence System VIP includes:

  • System Testbench Generator allows users to describe their testbench topology through IP-XACT or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation. 
  • System Traffic Library provides users with rich portable stimulus tests for common SoC domains including coherency, performance, PCIe, and NVMe subsystems, which run seamlessly in simulation, emulation, and final silicon. These libraries are integrated with Cadence VIP and Accelerated VIP (AVIP) for fast bring-up.
  • System Performance Analyzer offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals.  
  • System Verification Scoreboard provides data and cache-coherency checkers, which allow users to check data consistency across the system, supporting both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals, and is integrated with Cadence VIP and AVIP.

Using System VIP, Cadence customers creating hyperscale, automotive, mobile, and consumer SoCs can automate chip-level verification and improve efficiency by ten times over existing homegrown methodologies.

News ReleasesVIEW ALL
  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution 10/13/2020

Blogs VIEW ALL
Customers

“We’ve reduced some of the complex SoC verification challenges, especially around IO peripherals. By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”

Tran Nguyen, director of Design Services at Arm.

Resource Library

Video (5)

  • Accelerating SoC Verification Throughput with System VIP
  • Improve SoC-Level Verification Efficiency by Up to 10X with System VIP
  • Smart Verification Technology and Solutions
  • Cadence Delivers Verification Throughput
  • Introduction to System VIP

Press Releases (1)

  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution

White Paper (2)

  • Addressing the Challenge of Verifying System-Level Performance
  • System-Level Coherency Verification Challenges
VIEW ALL

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