- Up to 10X gain in chip-level verification efficiency
- Automatically generates chip-level testbenches for complex Arm, x86, and RISC-V based SoCs
- Jump-starts SoC testing with rich libraries of tests for SoC coherency, performance bottleneck identification and more
- Automated SoC level analysis, checking and reporting
- Portable across simulation, emulation, and prototyping verification engines
As SoC design complexity continues to increase, verification of the fully assembled chip with all its IP components, buses, and interfaces has become the critical path to tape out. Chip-level testbench creation, bus traffic generation, bus performance bottleneck identification, and data and cache coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Missed performance bottlenecks can expose architectural-level oversights late in the project and covering all corner cases for cache coherency across multiple parallel compute engines can take months.
Cadence® System-Level Verification IP (System VIP) takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. It consists of a suite of tools and libraries, each working seamlessly with Cadence’s simulation, emulation, and prototyping engines.
Cadence System VIP includes:
- System Testbench Generator allows users to describe their testbench topology through IP-XACT or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation.
- System Traffic Library provides users with rich portable stimulus tests for common SoC domains including coherency, performance, PCIe, and NVMe subsystems, which run seamlessly in simulation, emulation, and final silicon. These libraries are integrated with Cadence VIP and Accelerated VIP (AVIP) for fast bring-up.
- System Performance Analyzer offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals.
- System Verification Scoreboard provides data and cache-coherency checkers, which allow users to check data consistency across the system, supporting both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals, and is integrated with Cadence VIP and AVIP.
Using System VIP, Cadence customers creating hyperscale, automotive, mobile, and consumer SoCs can automate chip-level verification and improve efficiency by ten times over existing homegrown methodologies.
“We’ve reduced some of the complex SoC verification challenges, especially around IO peripherals. By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”
Tran Nguyen, director of Design Services at Arm.