Overview
Accelerating SoC Verification Tasks
The Cadence System VIP solution is a comprehensive suite of tools and libraries designed to assist SoC integrators in overcoming various challenges. This solution consists of four major components aimed at addressing the diverse challenges faced by modern SoC verification engineers.
By utilizing established verification engines such as simulation, hardware acceleration, and FPGA prototyping, the System VIP components offer testbench automation, pre-built portable stimulus content, performance analysis, and a system-level data integrity checker.
Cadence System-Level Verification IP
Chip-level test and testbench generation with advanced analytics
Key Benefits
Up to 10X Gain in Chip-Level Verification Efficiency
Automatic Testbench Generation and Analysis
Automatically generates chip-level testbenches for complex Arm®-, x86-, and RISC-V-based SoCs and automates SoC-level analysis, checking, and reporting
Comprehensive Test Libraries
Jump-starts SoC testing with rich libraries of tests for SoC coherency, performance bottleneck identification, and more
Accelerated Verification Solution for Full DRAM
Accelerates IP-to-SoC-level verification for complex memory controllers, PHYs, and devices for LPDDR5x, DDR5, HMB3, and GDDR6 protocols
Seamless Portability Across Verification Engines
Portable across simulation, emulation, and prototyping verification engines
Offerings
Automate Chip-level Verification and Improve Efficiency
Using System VIP, Cadence customers creating SoCs in hyperscale, automotive, mobile, and consumer application SoCs can automate chip-level verification and improve efficiency tenfold over existing homegrown methodologies.
System Testbench Generator
System Testbench Generator allows users to describe their testbench topology through IP-XACT or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation.
System Traffic Library
System Traffic Library provides users with rich portable stimulus tests for common SoC domains, including coherency, performance, PCIe®, and NVMe subsystems, which run seamlessly in simulation, emulation, and final silicon. These libraries are integrated with Cadence VIP and Accelerated VIP (AVIP) for fast bring-up.
System Performance Analyzer
System Performance Analyzer offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals.
System Verification Scoreboard
System Verification Scoreboard provides data and cache-coherency checkers, allowing users to check data consistency across the system and supporting both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals and is integrated with Cadence VIP and AVIP.
See What Customers Have to Say
“We’ve reduced some of the complex SoC verification challenges, especially around IO peripherals. By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”
Tran Nguyen, director of Design Services at Arm.
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