Metric-Driven Verification Signoff

Functional verification entails changing the state of a logic design and measuring that the response generated by the design is correct. Verification environments change the state of designs by driving stimulus in the form of directed or constrained random inputs. But when are you done? In verification, signoff is the process of defining criteria, and objectively measuring metrics against the criteria as the development progresses, until they match.

Metric-Driven Signoff is a unique Cadence^® methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development. While milestones and metrics vary by design type and end application, the final verification signoff will at, a minimum, contain the criteria and metrics within a flexible, human-readable, user-defined organizational structure. Automated data collection, project tracking, dashboards, and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.

Common pre-silicon IC stages will often consist of the following milestones leading to signoff.

Designer Handoff Milestone

The designer’s checklist will incorporate basic functional and structural checks. The most fundamental of these checks are sanity tests, FSM tests, and lint checking, often adding dynamic assertions to verify key design properties. Tools used at this stage normally include:

• Xcelium^™ Parallel Simulator – Lint, assertions, V/VHDL tests
• JasperGold^® Formal Verification Platform – SuperLint, CDC, and Property Apps
• SimVision^™ Debug – Waveform debugging
• Indago^™ Debug Platform – Waveform and Smartlog debugging
• Cadence Integrated Metric Center – FSM and coverage

IP Verification Milestone

From designer handoff, verification engineers will utilize the industry-standard Metric-Driven Verification (MDV) methodology for automating measurement compared to the goals. Criteria are captured in an executable verification plan, and metrics are collected after tests are run, then back-annotated to this plan. For IP designs, metrics will typically be around coverage (functional and code), regression tests, bug rate, and corner cases, and often augmented with formal techniques from the JasperGold platform. The vPlan within the vManager™ Metric-Driven Signoff Platform is used to organize data and automate the data collection. Tools used at this stage may include:

• Xcelium Parallel Simulator - UVM, assertions, V/VHDL tests
• JasperGold Formal Verification Platform – Unreachability, Property, Coverage Apps
• Indago Debug Platform (and Indago Protocol Debug App) – Waveform, Smartlog, and class-based debugging
• vManager Metric-Driven Signoff Platform – vPlan, regressions, metrics, coverage

SoC Verification Milestone – Verification teams will utilize the proven multi-engine Metric-Driven Verification methodology for combining data from many different tools and technologies. The SoC signoff metrics include all IP-level metrics, adding toggle coverage, fault coverage, connectivity, register, integration tests, analog or mixed-signal tests, full-chip use cases, power, performance, and chip benchmarks. The vPlan within the vManager platform is used to organize data and automate the data collection. Tools used at this stage may include:

• JasperGold Formal Verification Platform – Connectivity, Register, Xprop, Property Apps
• Xcelium Parallel Simulator – V/VHDL tests, fault testing/coverage
• Cadence Interconnect Workbench – On-chip bus performance
• Palladium^® Z1 Enterprise Verification Platform – Hardware/software integration testing platform
• Perspec^™ System Verifier – Software-driven tests / use-cases
• Indago Portable Stimulus Debug App – Software-driven use-case debugging
• Indago Embedded Software Debug App –Initialization software and software-driven test debugging
• Indago Debug Platform – Waveform, RTL, and low-power debugging
• SimVision Debug – Mixed-signal debugging
• Virtuoso^® ADE Verifier – Analog or mixed-signal tests
• vManager Metric-Driven Signoff Platform – vPlan, regressions, metrics, coverage