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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
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          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
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          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
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          • Virtuoso Layout Suite
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          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
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          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
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          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
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          • Clarity 3D Solver Cloud
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          • AWR Free Trial
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        • PRODUCT CATEGORIES
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          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
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          • Allegro X Design Platform
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        • Hyperscale Computing
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
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        • Photonics
        • RF / Microwave
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        • Automotive
        • Hyperscale Computing
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Metric-Driven Verification Signoff

Improving verification predictability, productivity, and quality 

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Key Benefits

  • Improved verification predictability with automated data collection and reporting
  • Fastest turnaround time from regression to bug triage and design debug
  • Clear signoff criteria ensuring consistent quality with traceable metric-based results

Functional verification entails changing the state of a logic design and measuring that the response generated by the design is correct. Verification environments change the state of designs by driving stimulus in the form of directed or constrained random inputs. But when are you done? In verification, signoff is the process of defining criteria, and objectively measuring metrics against the criteria as the development progresses, until they match.

Metric-Driven Signoff is a unique Cadence® methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development. While milestones and metrics vary by design type and end application, the final verification signoff will at, a minimum, contain the criteria and metrics within a flexible, human-readable, user-defined organizational structure. Automated data collection, project tracking, dashboards, and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.

Common pre-silicon IC stages will often consist of the following milestones leading to signoff.

Designer Handoff Milestone

The designer’s checklist will incorporate basic functional and structural checks. The most fundamental of these checks are sanity tests, FSM tests, and lint checking, often adding dynamic assertions to verify key design properties. Tools used at this stage normally include:

  • Xcelium™ Parallel Simulator – Lint, assertions, V/VHDL tests
  • JasperGold® Formal Verification Platform – SuperLint, CDC, and Property Apps
  • SimVision™ Debug – Waveform debugging
  • Indago™ Debug Platform – Waveform and Smartlog debugging
  • Cadence Integrated Metric Center – FSM and coverage

IP Verification Milestone

From designer handoff, verification engineers will utilize the industry-standard Metric-Driven Verification (MDV) methodology for automating measurement compared to the goals. Criteria are captured in an executable verification plan, and metrics are collected after tests are run, then back-annotated to this plan. For IP designs, metrics will typically be around coverage (functional and code), regression tests, bug rate, and corner cases, and often augmented with formal techniques from the JasperGold platform. The vPlan within the vManager™ Metric-Driven Signoff Platform is used to organize data and automate the data collection. Tools used at this stage may include:

  • Xcelium Parallel Simulator - UVM, assertions, V/VHDL tests
  • JasperGold Formal Verification Platform – Unreachability, Property, Coverage Apps
  • Indago Debug Platform (and Indago Protocol Debug App) – Waveform, Smartlog, and class-based debugging
  • vManager Metric-Driven Signoff Platform – vPlan, regressions, metrics, coverage

SoC Verification Milestone – Verification teams will utilize the proven multi-engine Metric-Driven Verification methodology for combining data from many different tools and technologies. The SoC signoff metrics include all IP-level metrics, adding toggle coverage, fault coverage, connectivity, register, integration tests, analog or mixed-signal tests, full-chip use cases, power, performance, and chip benchmarks. The vPlan within the vManager platform is used to organize data and automate the data collection. Tools used at this stage may include:

  • JasperGold Formal Verification Platform – Connectivity, Register, Xprop, Property Apps
  • Xcelium Parallel Simulator – V/VHDL tests, fault testing/coverage
  • Cadence Interconnect Workbench – On-chip bus performance
  • Palladium® Z1 Enterprise Verification Platform – Hardware/software integration testing platform
  • Perspec™ System Verifier – Software-driven tests / use-cases
  • Indago Portable Stimulus Debug App – Software-driven use-case debugging
  • Indago Embedded Software Debug App –Initialization software and software-driven test debugging
  • Indago Debug Platform – Waveform, RTL, and low-power debugging
  • SimVision Debug – Mixed-signal debugging
  • Virtuoso® ADE Verifier – Analog or mixed-signal tests
  • vManager Metric-Driven Signoff Platform – vPlan, regressions, metrics, coverage

Metric Driven Signoff

Metric-driven signoff is defined as the final stage of all design and functional tests prior to physical implementation or coinciding with tapeout. The signoff stage includes all milestones and metrics from previous stages, plus adds all final structural checks such as clocking and low power. This final signoff stage will add gate-level tests, state machine (FSM), clock (CDC), synthesis, X-prop, failure mode (fault) testing, pre-silicon power measurements, and more as required. The vPlan (figure 1) and vManager platform can be used to collect and organize this data and enable a comprehensive Metric-Driven Signoff environment, with automatic data collection, manual checklists, and manual test result entry. Tools used at this stage may include:

  • Xcelium Parallel Simulator - Multi-core for GLS, low power, and built-in self test (BIST)
  • Genus™ Synthesis solution – Synthesis solution
  • Conformal® technologies – LEC, CDC, and low-power checks
  • Joules™ RTL Power Solution – RTL power estimations
  • vManager Metric-Driven Signoff Platform – vPlan, regressions, metrics, coverage
Figure 1 – Metric Driven Signoff Plan from vManager

TRAINING COURSES

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