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Embedded Software

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  • PRODUCTS
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      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
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        • Synthesis
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        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
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      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
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        • Layout Verification
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        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
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        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
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        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
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        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
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        • What's New in Allegro
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        • AI / Machine Learning
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Perspec System Verifier

Improves system-level test development by up to 10X

Read Datasheet Read PSS White Paper
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Key Benefits

  • 10X productivity creating SoC tests for complex system scenario verification
  • Correct-by-construction generation of complex concurrent multi-core/multi-threaded tests
  • Verify more corner cases with automatic use-case amplification of state space and timing exploration on the fastest verification engines
  • Easy portability of test intent and test suite to derivative projects
  • Supports Accellera Portable Test and Stimulus Specification (PSS) 1.0
  • Downloadable PSS Methodology and Library: Includes documentation of the library, PSS best practices, and practical examples, plus the PSS source for the library. Request Download

Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests 10X faster using this platform solution. In addition, with its integrated debugging capability, you’ll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.

Figure 1: Perspec System Verifier

 

By applying an appropriate level of abstraction, the Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power.

The platform is portable, supporting reuse across:

  • SoC scope, from IP to the system level, including hardware-aware software
  • Domain experts create the model and describe scenarios, enabling verification and validation engineers to create system-wide tests
  • Generated tests run out of the box on all Cadence verification engines

Using the Perspec System Verifier, you'll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You'll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

Key Features

  • Downloadable PSS Methodology and Library: includes documentation of the library, PSS best practices, and practical examples, plus the PSS source for the library. Request Download
  • Goal-directed and true constraint solving
  • Multi-platform, multi-language solution leveraging existing standards and proven techniques
  • Automatic use-case amplification of state space and timing exploration on fast verification engines
  • Connect portable stimulus to UVM testbenches for IP and subsystem verification and stimulus portability
  • Coverage and automatic filling capabilities
  • Debug and coverage logging built into the generated C tests to speed both debug and analysis of coverage results
Figure 2: Make complex generated tests easy to understand

Customer Testimonials

NOTE: A Cadence account is required to access the presentation files.

  • Using PSS: An Automotive Case Study by Infineon Technologies
  • SoC Power Management Test Scenarios with Portable Stimulus by AMD
  • PSS in Real Life by Texas Instruments
  • Enable Complex CPU System’s Coverage Closure by SW-Driven Stimulus with Structural Coverage Beyond Accelerated Emulator by MediaTek
  • Automated Test Generation to Verify CPU Subsystem for System Level Low Power Management by Perspec by MediaTek
  • Make Stimuli Portable by Using Perspec System Verifier by Texas Instruments
  • Cadence Perspec System Verifier Usage at Sub-System/SoC/Silicon Level for Infineon Aurix Microcontrollers by Infineon
  • Cadence Perspec System Verifier on a Real SoC Verification of a MSP430 Mixed-Signal Microcontroller by Texas Instruments
  • Enabling Verification of Complex System Scenarios Using Perspec System Verifier by STMicroelectronics
  • Automated Test Generation to Verify IP Modified for System Level Power Management by STMicroelectronics
  • Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier by Renesas

Contact Us

TRAINING COURSES

Create intelligent tests for your SoC and system software that are tailored to your design and can be portable across simulation, emulation and post silicon.

TI Verification Expert Shares Their PSS UVM Synergy Experience

EEJournal Chalk Talk on Perspec System Verifier

  • Related Products

    • Cadence Verification Suite
    • Indago Embedded Software Debug App
    • Xcelium Logic Simulation
    • Palladium Z1 Enterprise Emulation Platform
    • Protium S1 Desktop Prototyping Platform
    • vManager Verification Management
Videos

SoC Verification with Perspec System Verifier

Introduction to vManager High Availability Architecture

TI Verification Expert Shares Their PSS UVM Synergy Experience

Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction

Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo

Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions

Cadence Perspec System Verifier SW Driven SoC Verification Automation

Mike Bartley, CEO of T&VS, on Portable Stimulus

DAC 2017 Report on Accellera Portable Stimulus Specification

AMIQ Eclipse IDE for Perspec Portable Stimulus

Texas Instruments - Using the Perspec Solution

News ReleasesVIEW ALL
  • Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development 05/26/2020

  • Cadence Delivers Portable Test and Stimulus Methodology and Library 07/17/2019

  • Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing 10/16/2018

  • Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0 06/26/2018

  • Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier 03/22/2017

Blogs VIEW ALL
Customers

We found that the Perspec technology easily detected issues caused by complex combinations of power mode settings and transitions. The technology can help us dramatically improve productivity and deliver our designs to IoT application developers much faster.

Toshinori Inoshita, Renesas

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With the Perspec approach we get a lot of interesting scenarios “for free” which are difficult to achieve in a directed test. … In case of failures, the scenario viewer helps to understand the intended execution flow.

Thorsten Klose, Infineon

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[It was] easy to generate complex scenarios using [Perspec] Composer drag and drop composition and scenario completion. [The] graphical scenario representation enables collaboration.

Smitha Kaginele and Murthy Hari, Microsemi

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This [Perspec] flow facilitates [absorption of] late design changes rapidly due to automation in the testbench and test case generation.

Vivek Goyal and Vijay Rajan Machingauth, Samsung

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[Perspec] Verification Engineer increased confidence in power sequence support. [This] methodology could be applied to any low-power (LP) verification.

Christophe Lamard, STMicroelectronics

Read More or View All Customers

[Perspec] system model changes can easily regenerate all test cases. Generated stimulus code is very well readable based on templates with the same look and feel as traditional stimuli.

Frank Donner, Texas Instruments

Read More or View All Customers

Perspec improves RTL regression efficiency and quality, ...[and] enables software/hardware co-verification.

Hsuan-Ming Chou, Osmond Yao, and Dennis Hsu, MediaTek

Read More or View All Customers

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