Perspec System Verifier

Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence^® Perspec^™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests 10X faster using this platform solution. In addition, with its integrated debugging capability, you’ll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.

By applying an appropriate level of abstraction, the Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power.

The platform is portable, supporting reuse across:

• SoC scope, from IP to the system level, including hardware-aware software
• Domain experts create the model and describe scenarios, enabling verification and validation engineers to create system-wide tests
• Generated tests run out of the box on all Cadence verification engines

Using the Perspec System Verifier, you'll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You'll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

Key Features

• Downloadable PSS Methodology and Library: includes documentation of the library, PSS best practices, and practical examples, plus the PSS source for the library. Request Download
• Goal-directed and true constraint solving
• Multi-platform, multi-language solution leveraging existing standards and proven techniques
• Automatic use-case amplification of state space and timing exploration on fast verification engines
• Connect portable stimulus to UVM testbenches for IP and subsystem verification and stimulus portability
• Coverage and automatic filling capabilities
• Debug and coverage logging built into the generated C tests to speed both debug and analysis of coverage results

Customer Testimonials

NOTE: A Cadence account is required to access the presentation files.

• Using PSS: An Automotive Case Study by Infineon Technologies
• SoC Power Management Test Scenarios with Portable Stimulus by AMD
• PSS in Real Life by Texas Instruments
• Enable Complex CPU System’s Coverage Closure by SW-Driven Stimulus with Structural Coverage Beyond Accelerated Emulator by MediaTek
• Automated Test Generation to Verify CPU Subsystem for System Level Low Power Management by Perspec by MediaTek
• Make Stimuli Portable by Using Perspec System Verifier by Texas Instruments
• Cadence Perspec System Verifier Usage at Sub-System/SoC/Silicon Level for Infineon Aurix Microcontrollers by Infineon
• Cadence Perspec System Verifier on a Real SoC Verification of a MSP430 Mixed-Signal Microcontroller by Texas Instruments
• Enabling Verification of Complex System Scenarios Using Perspec System Verifier by STMicroelectronics
• Automated Test Generation to Verify IP Modified for System Level Power Management by STMicroelectronics
• Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier by Renesas