Document
Overview
Improve System-Level Test Development by Up to 10X
The Cadence Perspec System Verifier is a portable stimulus and system-on-chip (SoC) verification solution. It improves SoC quality and saves time by reducing the effort needed to define complex SoC-level use cases. It amplifies the exploration of use-case state space and timing on fast platforms, automates system use-case generation based on coverage, bridges UVM and SoC verification methodology, and reduces the time required to reproduce, debug, and fix complex SoC-level bugs.
Key Benefits
Increase Productivity by Creating Verification Tests of Complex System Scenarios
Enhanced Test Construction
Leverages correct-by-construction methodologies to generate complex, concurrent tests for multi-core and multi-threaded environments, ensuring tests are built accurately from the outset
Comprehensive Corner-Case Verification
Automatic use-case amplification alongside state space and timing exploration to rigorously verify a broader spectrum of corner cases on high-speed verification engines
Seamless Test Portability
Offers easy transferability of test intent and entire test suites to derivative projects, streamlining the process for future applications
Standard Compliance and Support
Fully supports the Accellera Portable Test and Stimulus Specification (PSS), aligning with industry standards for easier integration and usage
Features
The PSS Methodology and Library Come with a Guide, Best Practices, Examples, and PSS Library Source
Products
Automatic Use-Case Amplification of State Space and Timing Exploration on Fast Verification Engines
Customer Stories