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CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
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        • 5G Systems and Subsystems
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        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
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        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Cadence Specman Elite

Faster and higher quality verification at block, chip, and system levels

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Key Benefits

  • Eliminates misrepresentations that lead to bug escapes
  • Provides rapid environment construction, scalability, and reuse
  • Automates test generation with up to 5X faster runtime

Cadence® Specman® Elite automates testbench generation and reuse, providing multi-language support and an advanced debug option. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology (UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established verification flows. It also provides an environment for working with, compiling, and debugging testbench environments written in the e language.

Cadence Specman Elite uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its functional coverage analysis capability drives verification using the metric-driven verification methodology. With automated testbench generation, you can boost verification productivity at block, chip, and system levels. 

The Cadence Specman Elite hardware verification language is supported on industry-standard simulators. As with other languages and standards, the Cadence Xcelium™ Parallel Logic Simulation's native compiler for IEEE 1647 e language provides superior runtime performance, multi-language support including Accellera UVM-ML OA, and advanced debug capabilities.

Specman Advanced Option

Available as an add-on to Cadence Enterprise Specman simulator, the Specman Advanced Option combines dynamic loading and reseeding techniques (both available in e) to greatly boost verification and debug productivity. You can run a simulation up to a certain point, save its state, and resume it in multiple processes later on. You can restore simulation states and reseed them to increase coverage, and also dynamically load new files after restoring to guide future results.

Bypassing lengthy start-up functionality, the Specman Advanced Option allows you to quickly locate the most meaningful portion of your simulations; achieve higher functional coverage; reduce test development and debug cycles; reduce regression runs; and save hundreds of simulation hours.

Key Features

  • Captures executable specifications to eliminate misrepresentations that lead to bug escapes
  • Leverages the e language’s unique aspect-oriented programming (AOP) capabilities for rapid environment construction, scalability, and reuse
  • The “IntelliGen” AOP constraint solver automates test generation with up to 5X faster runtime, unprecedented distribution control, and scalability for more than 1 billion logic gate devices
  • Automates data and assertion checking for faster debug
  • Tracks industry-standard coverage metrics (functional, transactional, HDL) for higher verification quality
  • Supports a proven metric-driven verification solution that applies UVM-MS for digital-centric mixed-signal verification to achieve first-pass success
  • Creates reusable sequences and multi-channel virtual sequences on top of an e verification environment
  • Comprehensive language support includes e, Open Verification Library (OVL), OVM class library, UVM class library, SystemC, SystemVerilog, Verilog, VHDL, PSL, SVA, C/C++ models, MATLAB models, and analog models in Verilog-A, VHDL-A, wreal, and SPICE
  • Works with all major simulators, with a high-speed direct kernel interface when used inside Xcelium Parallel Logic Simulation

Contact Us

TRAINING COURSES

Massive SoC Designs Open Doors to New Era in Simulation

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TI Verification Expert Shares Their PSS UVM Synergy Experience

Tapping into UVM ML to Support Reuse in Multi-Language Verification Environment

  • Related Products

    • Xcelium Logic Simulation
    • Cadence Verification Suite
    • vManager Verification Management
    • Indago Debug Analyzer
    • SimVision Debug
    • Perspec System Verifier
    • Verification IP
Videos

Achieving Better-Quality Results with Specman Elite

Mahesh Soni, Specman Expert on Leveraging the Testcase Generation Utility

Using the Specman Profiler

Leveraging Specman for Verification

Specman Tips & Tricks: Save, Restart & Dynamic Load with Specman

Specman Tips & Trick, e-HDL types compliance checks.

Specman: Fastest Patches on Earth

Orit Kirshenberg - Expert Insights Video

Leveraging Specman for Signoff

Nadav Eden – Specman Expert Insights Video

Yoav Lurie—Specman Expert Insights Video

Extoll - Dr. Niels Burkhardt—Specman Expert Insights video

The People Behind Range Generated Field (RGF) - Specman 18.03

MultiPhy Verifies Diverse Blocks Quickly with Specman + MATLAB Flow

Latest News for Cadence Specman Elite - January 2018

Specman Temporal Options

Specman - 5 minutes on Methods Extensions

Sequences 101

Virtual Sequences

Writing Sequences Tips

Performance and Debug – Get Both, Using Specman

News ReleasesVIEW ALL
  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution 10/13/2020

  • Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform 08/18/2020

  • Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions 08/12/2020

  • Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development 05/26/2020

  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

Blogs VIEW ALL
Customers

SystemVerilog is not just an extended version of Verilog. While the naming was successful, it's actually a new object-oriented language. More than two-thirds of the [SystemVerilog] language is actually something new. Designers have to learn what object-oriented is all about.

Michael Blech, PMC

Comparing ‘e’ and SystemVerilog is like comparing a screwdriver to a knife…Knife was designed to cut food, but it can also be used to drive screws with less efficiency.

Geoffrey Faurie, STMicroelectronics

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