Achieving a predictable path to verification closure requires automated planning and metrics management with comprehensive coverage at block, chip, and system levels. Cadence® technology tracks the progress of an evolving design against its functional, performance, and schedule objectives simultaneously. It automates the deployment of simulation runs, analyzes failures and coverage data, and guides the steps toward closure.
Our vManager™ Metric-Driven Signoff Platform, a first-of-its-kind automated verification planning and management solution, is the lead tool in this flow. The tool deploys execution runs, sets up analysis views, organizes and debugs errors, and generates additional verification scenarios automatically. Using the vManager Metric-Driven Signoff platform, you can improve your design quality while also enhancing productivity, predictability, controllability, and coordination of your functional verification environment.