The Cadence® Jasper™ FSV App complements the Cadence Safety Solution by adding fault qualification and propagation analysis to assist and improve overall safety analysis. There are two use models:
Integrated with fault simulation: The Jasper FSV App runs as part of a fault campaign and analyzes the fault list prior to fault injection, to reduce the fault set by marking faults as untestable or unobservable per simulation test. This highly automated flow allows safety verifiers to significantly reduce fault simulation time while improving coverage metrics.
Interactive formal fault analysis: The Jasper FSV App analyzes fault propagation to provide improved structural and functional visualization of propagation paths, and stronger formal checks to improve fault classification in order to meet or exceed safety specifications like ISO 26262 or DO-254.
These stronger checks answer questions like "Is a propagated fault always detected at the checker?" and “Can a fault ever propagate to a functional output?”, giving definitive answers where, in the case of fault simulation alone, these depend on the quality of the associated testbench. Results are presented in an interactive GUI mode for safety designers and can be exported in text or HTML format.
The interactive debug capabilities allow you to debug issues with fault propagation, or fault unobservability (like propagation barriers), using a schematic viewer for structural analysis and the Jasper Visualize™ Interactive Debug Environment’s waveform for formal “what-if” analysis.
Formal fault injection and propagation analysis can also be used in security verification, complementing the Jasper Security Path Verification (SPV) App by modeling direct attacks (by laser or other EM radiation for example) on internal circuitry.
Key Features
- Structural analysis for fault testability and observability
- Formal fault propagation analysis to determine whether injected faults always, sometimes, or never reach checker outputs or functional outputs
- Interactive fault propagation debug using structural and formal analysis, schematic viewer, and Visualize waveform viewer
- Supports RTL and gate- level designs
- Interactive or batch modes are fully supported
