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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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      • Technologies
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • Support Process
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Jasper LPV App

  • Overview

Key Benefits

  • Significantly reduces time, cost, and risks for low-power design verification
  • Requires no knowledge of formal or assertions
  • Automatically checks design structure and behavior, power intent, and low-power design guidelines

Enabling exhaustive verification of design functionality with static and dynamic power optimization techniques, the Cadence® Jasper™ Low-Power Verification (LPV) App is the only dedicated formal solution for low-power functional verification. Unlike non-exhaustive simulation-based approaches, the JasperGold LPV App automatically generates assertions that verify that the power description matches the power intent and guidelines specifications in IEEE 1801 standard Unified Power Format (UPF). Then, the app exhaustively verifies that the power modifications did not create any new hazards and are consistent and correct.

Low-power design and optimization techniques can significantly impact the structural and behavioral elements of your original design. These techniques can lead to the need for you to verify the safe entry and exit of all possible low-power modes, in addition to the functional behavior of the design under test (DUT). Because of this, simulation-based verification is often insufficient. An exhaustive formal verification approach is the most effective way to reduce the risk of a fatal bug escape.

With its built-in automation and debug capabilities, the Jasper LPV App can significantly reduce the design time, cost, and risks from low-power design complexity compared with traditional approaches. Because the app creates a power-aware internal register-transfer level (RTL) model, this model can also be input to other Jasper Apps for compelling power-aware static and functional verification analyses.

The Jasper LPV App takes as input the DUT RTL and then uses the corresponding power-intent specifications in UPF to transform the RTL to make it power-aware. With this "new" power-aware internal model, you can:

  • Automatically check the design structure and behavior, power intents, and low-power design guidelines
  • Verify the interplay between design elements defined in the power description (e.g., isolation and state retention cells) and design elements defined in the RTL description (e.g., clock and control signals) via automatically generated SystemVerilog Assertions
  • Export this power-aware RTL model and data to other JasperGold Apps for compelling power-aware static and functional verification analyses

By using the Jasper LPV App, you can eliminate the need to use traditional approaches such as spreadsheet analysis, automated structural analysis, manual functional analysis, power-aware simulation, and power-related design rule checking (DRC). You won’t need a background in formal or assertions because all property creation and formal analyses are automated by the app. You will work with a familiar waveform display that you can further manipulate with the Jasper Visualize™ Interactive Debug Environment.

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TRAINING COURSES

  • Jasper RTL Apps

    • Jasper FPV App
    • Jasper Sequential Equivalence Checking App
    • Jasper Design Coverage Verification App
    • Jasper Coverage Unreachability App
    • Jasper X-Propagation Verification App
    • Jasper Control and Status Register App
    • Jasper Connectivity Verification App
    • Jasper Superlint App
    • Jasper Behavioral Property Synthesis App
    • Jasper Low-Power Verification App
    • Jasper Security Path Verification App
    • Jasper Clock Domain Crossing App
    • Formal VIP
    • Jasper FSV App
Xcelium Parallel Simulator

Industry's first production-proven multi-core simulator

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