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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • 5G Systems and Subsystems
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        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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JasperGold XPROP App

  • Overview

Key Benefits

  • Avoids issues from “X optimism” or “X pessimism”
  • Provides rapid X-propagation fault analysis
  • Requires no knowledge of formal or SVAs

Employing special formal engines with correct “X” semantics, the Cadence® JasperGold® X-Propagation Verification (XPROP) App analyzes your register-transfer level (RTL) design to ensure that no unexpected ‘X’ values emerge and propagate. The app automatically creates and executes checks for sources of, and conditions that lead to, unwanted Xs. A customized GUI provides rapid X-propagation fault analysis. And the best part? You don’t need to know assertion-based verification or SystemVerilog Assertions (SVAs).

The semantics of X are language and tool dependent. In RTL design, X tells the synthesis tool that it doesn't matter whether a 0 or 1 is assigned during logic optimization and in verification. But in simulation, X tells the simulator that a signal value is “unknown.” This mismatch in semantics and incomplete test vectors in simulation can hide bugs that are likely to show up in silicon no matter how careful you are about considering “X optimism” or “X pessimism.” 

The JasperGold XPROP App automatically creates exhaustive checks for unwanted Xs on various design elements, such as:

  • Clocks and resets to ensure that they are free of Xs
  • Control and data structures to see which areas of the code Xs can propagate to
  • Outputs to see if Xs can be propagated out of the design

The JasperGold XPROP App’s GUI is highly optimized for the desired workflow: a wizard guides the setup and configuration to control the source and targets for Xs. The debug waveform/CEX GUI always gives a concise failure trace with the path of the detected Xs from source to destination.

Key Features
  • The Fault Analysis view quickly points out the reason(s) for the X, significantly speeding up debug and reducing the effort needed to find X-related bugs
  • Combined with our powerful JasperGold Visualize™ Interactive Debug Environment, the app allows you to add or modify constraints on-the-fly to test out “what if?” scenarios before modifying the RTL
  • Provides higher throughput by allowing multiple proofs in parallel to be managed and tracked using the JasperGold ProofGrid™ Intelligent Resource Manager

Contact Us

TRAINING COURSES

  • JasperGold Formal Verification Platform

    • JasperGold Formal Verification Platform
    • JasperGold FPV App
    • JasperGold Sequential Equivalence Checking App
    • JasperGold Design Coverage Verification App
    • JasperGold Coverage Unreachability App
    • JasperGold X-Propagation Verification App
    • JasperGold Control and Status Register App
    • JasperGold Connectivity Verification App
    • JasperGold Superlint App
    • JasperGold Behavioral Property Synthesis App
    • JasperGold Low-Power Verification App
    • JasperGold Security Path Verification App
    • JasperGold Clock Domain Crossing App
    • Assertion-Based Verification IP
    • JasperGold FSV App

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