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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • China - 简体中文
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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
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        • AI / Machine Learning
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JasperGold Superlint App

Read White Paper
  • Overview
  • Customers

Key Benefits

  • Combines traditional RTL structural lint and formal analysis, deriving rich property-based functional checks from the RTL automatically
  • Helps eliminate common functional design errors ahead of full unit-level or chip-level verification
  • Fully integrated with the powerful Visualize debug environment, utilizing proven formal intelligence to reduce violation noise, speed debug, and improve waiver handling

Register-transfer level (RTL) designers often need to perform basic verification as soon as enough RTL is available, rather than waiting for testbench availability and before handing off the design to verification specialists. Assertion-based verification (ABV) can support an expedited workflow, but writing assertions demands specialized knowledge and can be very time-consuming even for experts.

Saving many weeks of tedious, error-prone work, the Cadence® JasperGold® Superlint App automatically generates high-value functional checks based on your RTL—no testbench or stimuli are required. This augments the wide range of structural lint and DFT checks that are also available with the JasperGold Superlint App. Doing this wide range of checks early during RTL development helps designers to do a much more comprehensive RTL signoff leading to significantly improved RTL quality. The JasperGold Superlint App is designed to be low noise and provides a lot of productivity features for designers to efficiently manage the violations.

Checks available in the JasperGold Superlint App include:

  • Comprehensive set of structural lint checks, e.g., naming, coding style, simulation-synthesis mismatch, synthesis
  • Comprehensive set of DFT checks (both shift and capture mode) to ensure design is testable
  • Best-in-class auto-formal checks, e.g., dead-code, FSM reachability/deadlock/livelock, bus contention, case, arithmetic overflow, and out-of-bounds index 

Bottom line: The JasperGold Superlint App helps eliminate common functional design errors and makes sure the code is clean before verification starts, improving design quality, and shortening the overall schedule.

Key Features

  • Interactive or batch modes are fully supported
  • Violations are grouped to enable efficient analysis 
  • Uses unique JasperGold Visualize™ Interactive Debug Environment to let you focus on disposition of violations and provides easy specification of waivers
  • Violation information and waivers are persistent for noise reduction during follow-on runs 
  • Context-sensitive debug capabilities are provided based on the type of violation, e.g., schematic for structural/DFT violations, FSM graph for FSM-related violations and waveform for auto-formal violations
  • Unique capability to leverage formal to refine lint results helps reduce noise and makes the violation analysis much more productive 

Contact Us

TRAINING COURSES

  • JasperGold Formal Verification Platform

    • JasperGold Formal Verification Platform
    • JasperGold FPV App
    • JasperGold Sequential Equivalence Checking App
    • JasperGold Design Coverage Verification App
    • JasperGold Coverage Unreachability App
    • JasperGold X-Propagation Verification App
    • JasperGold Control and Status Register App
    • JasperGold Connectivity Verification App
    • JasperGold Superlint App
    • JasperGold Behavioral Property Synthesis App
    • JasperGold Low-Power Verification App
    • JasperGold Security Path Verification App
    • JasperGold Clock Domain Crossing App
    • Assertion-Based Verification IP
    • JasperGold FSV App
Customers

"With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”

Hobson Bullman Vice President and General Manager, Technology Services Group, ARM

Read More or View All Customers

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