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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
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        • 5G Systems and Subsystems
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      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Jasper FSV App

Key Benefits

  • Significantly reduces fault simulation time and improves fault simulation coverage
  • Formally analyzes fault propagation to improve fault classification
  • Tightly integrated with Cadence functional safety flow
  • Interactive debug capabilities to understand fault propagation or propagation barriers

The Cadence® Jasper™ FSV App complements the Cadence Safety Solution by adding fault qualification and propagation analysis to assist and improve overall safety analysis. There are two use models:

Integrated with fault simulation: The Jasper FSV App runs as part of a fault campaign and analyzes the fault list prior to fault injection, to reduce the fault set by marking faults as untestable or unobservable per simulation test. This highly automated flow allows safety verifiers to significantly reduce fault simulation time while improving coverage metrics.

Interactive formal fault analysis: The Jasper FSV App analyzes fault propagation to provide improved structural and functional visualization of propagation paths, and stronger formal checks to improve fault classification in order to meet or exceed safety specifications like ISO 26262 or DO-254.

These stronger checks answer questions like "Is a propagated fault always detected at the checker?" and “Can a fault ever propagate to a functional output?”, giving definitive answers where, in the case of fault simulation alone, these depend on the quality of the associated testbench. Results are presented in an interactive GUI mode for safety designers and can be exported in text or HTML format.

The interactive debug capabilities allow you to debug issues with fault propagation, or fault unobservability (like propagation barriers), using a schematic viewer for structural analysis and the Jasper Visualize™ Interactive Debug Environment’s waveform for formal “what-if” analysis.

Formal fault injection and propagation analysis can also be used in security verification, complementing the Jasper Security Path Verification (SPV) App by modeling direct attacks (by laser or other EM radiation for example) on internal circuitry.

Key Features
  • Structural analysis for fault testability and observability
  • Formal fault propagation analysis to determine whether injected faults always, sometimes, or never reach checker outputs or functional outputs
  • Interactive fault propagation debug using structural and formal analysis, schematic viewer, and Visualize waveform viewer
  • Supports RTL and gate- level designs
  • Interactive or batch modes are fully supported

Contact Us

TRAINING COURSES

  • Jasper RTL Apps

    • Jasper FPV App
    • Jasper Sequential Equivalence Checking App
    • Jasper Design Coverage Verification App
    • Jasper Coverage Unreachability App
    • Jasper X-Propagation Verification App
    • Jasper Control and Status Register App
    • Jasper Connectivity Verification App
    • Jasper Superlint App
    • Jasper Behavioral Property Synthesis App
    • Jasper Low-Power Verification App
    • Jasper Security Path Verification App
    • Jasper Clock Domain Crossing App
    • Formal VIP
    • Jasper FSV App
Resource Library

Press Releases (1)

  • Cadence Introduces Comprehensive Safety Solution for Faster Certification of Automotive and Industrial Designs | Cadence

Solution (1)

  • Cadence Introduces Comprehensive Safety Solution for Faster Certification of Automotive and Industrial Designs | Cadence
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  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence and Intel Foundry Services Collaborate to Accelerate Innovation with Scalable and Proven Cadence Cloud Solutions 06/28/2022

  • Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies 06/21/2022

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