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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • 5G Systems and Subsystems
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        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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JasperGold UNR App

  • Overview

Key Benefits

  • Automatically and exhaustively explores the reachability of yet-to-be-hit cover points in the simulation coverage database
  • Exposes bugs with DUT by identifying unexpected unreachable points
  • Saves weeks of time and effort to achieve coverage closure metrics by eliminating true unreachable covers

Automating the previously tedious, time-consuming code coverage analysis process, the Cadence® JasperGold® Coverage Unreachability (UNR) App saves weeks of time to attain verification closure. The app takes a partially complete simulation coverage database and register-transfer level (RTL) code for the design under test (DUT) as inputs, and automatically generates properties to formally explore the reachability of uncovered cover points remaining in the database. The JasperGold UNR App can be readily used by simulation users with minimal formal verification experience.

When verification teams measure simulation coverage attained versus effort spent to create further simulation tests, the typical curve is initially steep and greatly flattens later on, signifying diminishing returns of adding new tests. A much greater effort is needed to create tests that increase “last mile” coverage significantly. The knee of this curve may occur anywhere in the 70-95% code coverage range, depending on the DUT. This is an optimal point to run the JasperGold UNR App.

Using the JasperGold UNR App, you can create properties to explore the reachability of the remaining points, identifying points that can be eliminated from further consideration and focusing on where further test creation efforts can be useful. Through this process of formal-assisted coverage closure, the JasperGold UNR App can save weeks of effort.

Key Features

  • Automatically generates properties to explore the reachability of yet-to-be-hit cover points in the simulation coverage database
  • Outputs a database of unreachable points for easy review, highlighting DUT or testbench bugs
  • Supports automatic merging of the set of reviewed and accepted unreachables with the simulation coverage database to improve coverage closure metrics
  • Supports Cadence’s Xcelium™ Logic Simulator, Unicov database, vManager™ Verification Management, and Integrated Metrics Center

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TRAINING COURSES

  • JasperGold Formal Verification Platform

    • JasperGold Formal Verification Platform
    • JasperGold FPV App
    • JasperGold Sequential Equivalence Checking App
    • JasperGold Design Coverage Verification App
    • JasperGold Coverage Unreachability App
    • JasperGold X-Propagation Verification App
    • JasperGold Control and Status Register App
    • JasperGold Connectivity Verification App
    • JasperGold Superlint App
    • JasperGold Behavioral Property Synthesis App
    • JasperGold Low-Power Verification App
    • JasperGold Security Path Verification App
    • JasperGold Clock Domain Crossing App
    • Assertion-Based Verification IP
    • JasperGold FSV App

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