Jasper CDC App

Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains, and signals are frequently transferred from one clock domain to another. In hardware, such lock domain crossing (CDC) signals are often subject to metastability effects that can cause functional failures. Traditional methods like register-transfer level (RTL) simulation or static timing analysis alone are not sufficient to verify that the data is transferred consistently and reliably across clock domains. As a result, many CDC-related bugs go undetected until the post-silicon verification stage, necessitating costly re-spins. Similar issues can occur with reset domain crossings (RDCs).

The Cadence^® Jasper^™ Clock Domain Crossing (CDC) App enables users to perform comprehensive CDC and RDC signoff. It automatically infers CDC intent from the design, along with clock and reset information captured either in the formal testbench or in SDC files. The Jasper CDC App comprehensively analyzes structural, functional, and reconvergence issues. Fully integrated with the Jasper Visualize™ Interactive Debug Environment, the Jasper CDC App also provides advanced CDC-specific debugging options, with efficient violation- and waiver-handling capabilities.

Key Features

• Comprehensive structural analysis for CDC and RDC issues
• Strong functional checks backed by best-in-class formal engines
• Metastability modeling and injection in both formal and simulation
• Best-in-class integrated debug environment
• Powerful Tcl interface for flexible custom report generation
• Tight integration with Cadence Xcelium™ Logic Simulation
• Constraint validation in formal and simulation
• Waiver validation using auto/safe waiver flow