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  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
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        • Automotive
        • AI / Machine Learning
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        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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JasperGold CONN App

  • Overview

Key Benefits

  • Captures complex specifications in familiar, human, and machine-readable formats
  • Automatically generates connectivity specification from known-good design for use on derivative designs (reverse connectivity)
  • Generates all properties automatically
  • Automatically black-boxes unnecessary IP blocks for connectivity verification
  • Performs exhaustive verification in hours vs. days or weeks
  • Fast debug via Visualize and QuietTrace technology

By capturing complex specifications in a familiar format, the Cadence® JasperGold® Connectivity Verification (CONN) App allows you to exhaustively verify the static, structural, temporal, and conditional connectivity of IP blocks inside a system on chip (SoC). Specifically, the app first takes the connectivity specification—captured in a comma-separated-values (CSV) file or an IP-XACT XML file—and the register-transfer level (RTL) design as inputs. Then the JasperGold CONN App automatically generates structural, behavioral, and temporal connectivity checks, exhaustively verifying if the connectivity is as specified. A utility is included so you can quickly black-box out unnecessary IP blocks to keep the analysis focused on connectivity, allowing the connectivity verification to scale readily to full chip-level.

While “correct-by-construction” tools and techniques go a long way, errors can still creep in due to unclear or erroneous specifications, the addition of low-power structures, built-in self-test (BIST), and JTAG support, or downstream changes/engineering change orders (ECOs) that weren’t fully propagated. In addition, connectivity of a sub-module that appears correct may prove to be erroneous in a larger scope.

The JasperGold CONN App performs exhaustive verification in hours, not the days or weeks common for simulation-based approaches. Unlike competitive formal connectivity apps that output noisy, hard to read counterexamples (CEX), the app’s JasperGold Visualize™ Interactive Debug Environment with QuietTrace™ debugging capabilityshows errors via “low-noise”, minimum-length CEX traces for high user productivity. Since creating the connectivity definition can be tedious and error-prone, the app can also extract connectivity from a golden RTL and verify any unintended changes in a subsequent RTL revision. The JasperGold CONN App is completely automated, so you won’t need to learn formal or SystemVerilog Assertions (SVAs).

Key Features

  • Supports all connectivity types: unconditional/static, constant and dynamic conditional, combinational value propagation without latencies, sequential value propagation with latencies and pipelined connections with multiple clocks and resets
  • Captures the connectivity description in open, human, and machine-readable CSV or IP-XACT XML files
  • Includes a utility to quickly black-box the internals of the design to focus the verification only on connectivity
  • Easy to fully automate this flow and run it in a regression mode
  • Reverse connectivity capability enables you to automatically create a high-level connectivity specification from your known-good design
  • Supports parallelism with our JasperGold ProofGrid™ Intelligent Resource Manager’s formal engine control utility

 

Contact Us

TRAINING COURSES

  • JasperGold Formal Verification Platform

    • JasperGold Formal Verification Platform
    • JasperGold FPV App
    • JasperGold Sequential Equivalence Checking App
    • JasperGold Design Coverage Verification App
    • JasperGold Coverage Unreachability App
    • JasperGold X-Propagation Verification App
    • JasperGold Control and Status Register App
    • JasperGold Connectivity Verification App
    • JasperGold Superlint App
    • JasperGold Low-Power Verification App
    • JasperGold Security Path Verification App
    • JasperGold Clock Domain Crossing App
    • Assertion-Based Verification IP
    • JasperGold FSV App

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