Overview

Verification Throughput for Pre-Silicon Software Verification

Cadence Protium prototyping platforms rapidly bring up an SoC or system prototype and provide a pre-silicon platform for early software development, SoC verification, system validation, and hardware regressions.

Key Benefits

Delivering High-Performance and High-Capacity Hardware for Software Development and Testing of Complex SoCs and Systems

High Performance

Highest-performance enterprise prototypes for testing software on multi-billion-gate designs

High Capacity

Provides capacity for multi-billion-gate designs by leveraging the industry’s largest production FPGA, the AMD VP1902 Versal Adaptive SoC

Fast Bring-Up

Quick bring-up from the Palladium system in a few days, fully automatic compile flow, and extensive debug and visibility

Verify the Full Software Stack

Provides at-speed performance needed to develop and test BIOS/firmware, OS, and application-level software

Use Models

Increase Productivity by Utilizing the Protium Platform Across Various Use Models

  • In-circuit prototyping
  • Hybrid prototyping with a virtual platform
  • Continuous at-speed data-capture
  • Early firmware development/software debug
  • Pre-silicon software/OS development
  • Hardware/software co-verification
  • System integration level test

Offerings

Protium X2 Enterprise Prototyping Platform

Protium X3 Enterprise Prototyping Platform

  • Scales to 48B gates
  • Modular compiler: Compiles in under 24 hours
  • 8X footprint reduction
  • 1.5X higher performance over Protium X2 system
  • Common front-end for all Palladium and Protium systems
  • Common virtual and physical interfaces with Palladium and Protium systems
  • Easy transition from previous-generation Protium systems

Protium X2 Enterprise Prototyping Platform

  • Leverages the Xilinx VU19P for FPGA prototyping
  • 2X capacity per rack and 1.5X speed over Protium X1 platform
  • Unified compile, testbench link, and interfaces with Palladium Z2 for quick bring-up
  • 2X higher debug throughput
  • 2X faster host-workstation connection
  • 2X faster memory access
  • Enhanced multi-user features

Protium Hybrid

The Helium Virtual and Hybrid Studio extends our emulation and prototyping systems by integrating virtual hybrid models with RTL in Palladium and Protium systems to increase effective performance, add capability, or improve effectiveness in selected use cases.

  • Increase effective performance by offloading already validated performance gating components such as third-party CPU cores
  • Enable system-level verification early by integrating the virtual platform models of components still under development
  • Improve effectiveness with system-level testing at unit-level capacity by integrating a single RTL with a system-level virtual platform

Apps

  • Job Scheduling App: An enterprise-scale flexible queue-based interface for dispatching emulation jobs with support for job prioritization and job starvation mitigation.
  • Video Analyzer App: A graphical view of graphical and video-based interfaces with a live view of real-time data supporting the capture, debug, analysis, and playback of waveform data.

Interfaces

  • Accelerated VIP and VirtualBridge Adapters: High-performance protocol IP that enables virtual driver- and application-level testing with the Palladium and Protium systems
  • Memory Model Portfolio: Industry-standard memory models for easy integration with the Palladium and Protium systems
  • Protium Daughtercards: Integrated ICE interfaces, external memory solutions, test equipment adapters, and debug with external data capture cards (DCC)
  • SpeedBridge Adapters and EDKs: Protocol interface solutions that enable efficient driver- and application-level testing and off-the-shelf, BIOS-optimized target hosts to enable integrated, unmodified OS and software
  • Virtual Debug and Physical JTAG: Enables users of third-party debuggers, including Lauterbach Trace32, Xtensa OCD, Arm Development Studio, Green Hills MULTI, and Open OCD, to access Palladium or Protium emulated processor cores via JTAG, DAP, and AMBA protocols

Access these tools on Cadence Cloud

Verified with Cadence

Learn how our customers use the Dynamic Duo to optimize workload distribution between verification, validation and pre-silicon software bring-up and adopt a shift-left methodology to accelerate their product development process.

 

AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo

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NVIDIA Embraces the Groundbreaking Technology, Dynamic Duo

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Related Products

Cadence Verification
Palladium Emulation
Helium Virtual and Hybrid Studio
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