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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • SUPPORT
      • SUPPORT
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      • SUPPORT
        • Support Process
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SimVision Debug

A unified graphical debugging environment

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Key Benefits

  • “Walks up” to any running simulation for interactive debugging
  • Offers interactive and/or post-process debug supporting OOP/AOP class-based debug environments

A unified graphical debugging environment within Cadence® Xcelium™ Parallel Logic Simulation, Cadence SimVision™ Debug supports signal-level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages. It also supports concurrent visualization of hardware, software, and analog domains.

SimVision Debug can be used to debug digital, analog, or mixed-signal designs written in Verilog, SystemVerilog, e, VHDL, and SystemC® languages or a combination thereof.

SimVision integrated debug supports signal-level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages, in addition to concurrent visualization of hardware, software, and analog domains.

SimVision Debug provides a unified simulation and debug environment that allows Xcelium Simulation to manage multiple simulation runs easily and to analyze both design and testbench behavior at any point in the verification process—regardless of the composition.

Throughout the design and verification flows, SimVision Debug provides source browsing, transaction and mixed-signal waveform analysis, complete code/transaction/ assertion coverage analysis, integrated display and debug of power behaviors, hardware analysis checks, and seamless connections to downstream implementation flows. APIs based on industry standards are available at all levels to enable user-defined checks and analysis. Design and testbench models can be interleaved in any language and any level of abstraction without the performance and integration overhead caused by co-simulation.

SimVision Debug comprises several analysis windows to address debug complexity. Some of these windows (available as toolbar buttons and menu choices) include:

  • The Properties window, which lets you manage the cursors, markers, expressions, and other debugging objects that you have created during your SimVision Debug session
  • The Design Browser window, which lets you monitor the signals and variables in the design
  • The Waveform window, which plots simulation data along an X and a Y axis. Data is usually shown as signal values versus time, but it can be any recorded data
  • The Source Browser, which gives you access to the design source code
  • The Schematic Tracer, which displays a design as a schematic diagram and lets you trace a signal through the design
  • The Memory Viewer, which lets you observe changes in the internal state of memory locations. During simulation, it also lets you set breakpoints, and force and deposit values to memory locations
  • The Watch window, which lets you monitor selected signals and variables in the design in a more concise form than the Design Browser
  • The Register window, which lets you use a free-form graphics editor to define any number of register pages, each containing a custom view of the simulation data
  • The Expression Calculator, which lets you define expressions, which combine signals to form buses, conditions, and virtual signals
Graphical view of SimVision window
SimVision Debug waveform window synchronized with the Design Browser and Source Browser windows
SimVision Debug displaying transactions in the waveform window synchronized with the Transaction Stripe Chart window

Unique Features of SimVision

  • Multi-language, mixed-signal support: SimVision Debug supports all IEEE and Accellera standards for digital, analog, or mixed-languages (Verilog, SystemVerilog, e, VHDL, SystemC/C/C++, or a combination). You can leverage SimVision Debug from the Virtuoso and/or Incisive environment. Analog and mixed-level behavioral abstractions of wreal, SystemVerilog reals, Verilog-AMS, and Verilog/VHDL are also supported.
  • Walk-up connections: SimVision Debug can “walk up” to any running simulation, allow you to interactively debug, and then detach from it to continue the simulation.
  • e/SystemVerilog class-based debug: SimVision Debug offers interactive and/or post-process debug that supports OOP/AOP class-based debug environments. It supports full Logical Path Name as well as unique class object handles (direct handle to object in memory). SimVision Debug also provides many innovative visualization capabilities to debug dynamic data in post-processing mode.
  • UVM awareness: Since the Universal Verification Methodology (UVM) defines class-based, transaction-driven testbenches, you need a debug environment centered on these elements. SimVision Debug enables you to access the environment through both the class inheritance and the instance trees. You can follow the simulation flow single-stepping through/over lines, method calls, and even into macros.
  • Transaction analysis: If the testbench uses transaction recording, debug becomes even easier. UVM provides automatic transaction recording so that you can view your test sequences. SimVision Debug adds a novel stripe chart view that allows you to visualize the sequential order of transactions across multiple streams.
  • Macro debug:SimVision Debug simplifies UVM debug by giving you visibility into expanded macro code, in-line with your source code while retaining original formatting. It also identifies nested macros, expands/collapses macros, and debugs annotated values for all macro variables.

Check out the SimVision Debug video series on our YouTube channel for additional insights.

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TRAINING COURSES

Xcelium Parallel Simulator

Industry's first production-proven multi-core simulator

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  • Related Products

    • Xcelium Logic Simulation
Resource Library

Press Releases (5)

  • Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
  • Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent
  • M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
  • Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
  • Cadence Redefines Verification Planning and Management with Incisive vManager Solution

Datasheet (1)

  • Embedded Software Debug App Datasheet

Customers Success (2)

  • Cadence and Melexis Success Story
  • Cadence and STMicroelectronics Success Story
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution 10/13/2020

  • Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform 08/18/2020

  • Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions 08/12/2020

  • Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development 05/26/2020

  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

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