Fast and Comprehensive Interactive and Post-Process Debug

Cadence Verisium Debug provides a modern, fast, and comprehensive graphical and shell-based debug capability across all Cadence verification engines. Natively integrated with the Cadence Verisium AI-Driven Verification Platform, it brings the power of AI to drastically cut debug time and accelerate time to market.

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AI-Powered Debug Solution for Fastest Bug Root Cause Analysis

Unified Debug Experience

Integrates natively with all Cadence verification engines and provides, optimized debugging GUI with a powerful and modern waveform viewer, source code browser, and SmartLog for a broad spectrum of debug needs, including RTL, gate level, testbench, low power, mixed signal, and embedded software.

Cut Debug Time Leveraging AI

Integrates with the Cadence Joint Enterprise Data and AI (JedAI) Platform and other Verisium Apps to enable AI-powered root cause analysis of bugs with simultaneous side-by-side comparison of passing and failing tests.

Fastest Waveform Bring-Up Time

Fast and compact waveform dumps directly from Cadence verification engines into the Cadence JedAI Platform with fast and scalable read performance during post-process debug.

User Apps

Provides a rich Python API interface to allow users to develop custom apps for functions, widgets, and flow integrations.

Features

Testbench Debug

Natively integrated with Xcelium Logic Simulator, Verisium Debug provides advanced, interactive, and post-process UVM SystemVerilog and Specman Elite/e-aware debug with constraint debugging, access to dynamic constructs, randomization process, and more.

RTL-and Gate-Level Debug

Verisium Debug provides advanced driver tracing, high-performance waveform viewer, fast design hierarchy navigation, detailed schematic, and powerful SmartLog technology.

Emulation and Prototyping Debug

Natively integrated with the Palladium emulation and Protium prototyping platforms, Verisium Debug delivers fast massively parallel multi-billion-gate capacity waveform dump and post-process debug.

Mixed Signal

Verisium Debug offers waveform, source code, and simulation control of mixed-signal nets and real number model-based SystemVerilog.

Low Power

Verisium Debug provides interactive post-process debug of low-power simulations with IEEE 1801/UPF and X-propagation, including waveform, source, schematic, and other advanced debug features specifically designed for low-power debug.

Embedded Software (ESW) Debug

Natively integrated with the Helium Virtual and Hybrid Studio, Verisium Debug offers simultaneous synchronized debug of RTL and embedded software, enabling rapid root cause analysis of bugs during hardware and software co-design.

Videos

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