Fast and Comprehensive Interactive and Post-Process Debug
Cadence Verisium Debug provides a modern, fast, and comprehensive graphical and shell-based debug capability across all Cadence verification engines. Natively integrated with the Cadence Verisium AI-Driven Verification Platform, it brings the power of AI to drastically cut debug time and accelerate time to market.
AI-Powered Debug Solution for Fastest Bug Root Cause Analysis
Unified Debug Experience
Integrates natively with all Cadence verification engines and provides, optimized debugging GUI with a powerful and modern waveform viewer, source code browser, and SmartLog for a broad spectrum of debug needs, including RTL, gate level, testbench, low power, mixed signal, and embedded software.
Cut Debug Time Leveraging AI
Integrates with the Cadence Joint Enterprise Data and AI (JedAI) Platform and other Verisium Apps to enable AI-powered root cause analysis of bugs with simultaneous side-by-side comparison of passing and failing tests.
Fastest Waveform Bring-Up Time
Fast and compact waveform dumps directly from Cadence verification engines into the Cadence JedAI Platform with fast and scalable read performance during post-process debug.
Provides a rich Python API interface to allow users to develop custom apps for functions, widgets, and flow integrations.
Natively integrated with Xcelium Logic Simulator, Verisium Debug provides advanced, interactive, and post-process UVM SystemVerilog and Specman Elite/e-aware debug with constraint debugging, access to dynamic constructs, randomization process, and more.
RTL-and Gate-Level Debug
Verisium Debug provides advanced driver tracing, high-performance waveform viewer, fast design hierarchy navigation, detailed schematic, and powerful SmartLog technology.
Emulation and Prototyping Debug
Natively integrated with the Palladium emulation and Protium prototyping platforms, Verisium Debug delivers fast massively parallel multi-billion-gate capacity waveform dump and post-process debug.
Verisium Debug offers waveform, source code, and simulation control of mixed-signal nets and real number model-based SystemVerilog.
Verisium Debug provides interactive post-process debug of low-power simulations with IEEE 1801/UPF and X-propagation, including waveform, source, schematic, and other advanced debug features specifically designed for low-power debug.
Embedded Software (ESW) Debug
Natively integrated with the Helium Virtual and Hybrid Studio, Verisium Debug offers simultaneous synchronized debug of RTL and embedded software, enabling rapid root cause analysis of bugs during hardware and software co-design.
New Cadence Xcelium Apps Accelerate Simulation-Based Verification for Automotive, Mobile and Hyperscale Designs
- 29 Jun 2022
- News Release
Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success
- 28 Jun 2022
- News Release
See What Customers Have to Say About the Verisium Debug
Our tight collaboration with Cadence confirms Verisium’s groundbreaking ability to automatically accelerate the effort to root cause bugs, and we are working with Cadence to expand deployment across our IP and SoC verification teams.
Chinh Tran, MediaTek
We see a great opportunity to leverage AI and big data to dramatically improve design and verification productivity. We are working closely with Cadence to deploy the Verisium platform on our mobile SoC designs and are already seeing impressive results to automatically triage and root cause bugs.
S. Brian Choi, Samsung Electronics
We have already observed a significant boost to functional verification productivity, leveraging Verisium AutoTriage, SemanticDiff and WaveMiner. Using the Verisium apps and the Cadence JedAI Platform, we aim to quickly achieve a dramatic productivity improvement in triaging and localizing bugs...
Mirella Negro Marcigaglia, STMicroelectronics