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    • DESIGN EXCELLENCE
    • Digital Design and Signoff
      Digital Design and Signoff Overview

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      Full-Flow Digital Solution Related Products A-Z

      Product Categories
      • Logic Equivalence Checking
        • Products
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • SoC Implementation and Floorplanning
        • Products
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • Functional ECO
        • Products
        • Conformal ECO Designer
      • Low-Power Validation
        • Products
        • Conformal Low Power
      • Synthesis
        • Products
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Virtuoso Digital Implementation
      • Power Analysis
        • Products
        • Joules RTL Power Solution
      • SDC and CDC Signoff
        • Products
        • Conformal Litmus
        • Conformal Constraint Designer
      • Silicon Signoff and Verification
        • Products
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • Library Characterization
        • Products
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • Test
        • Products
        • Modus DFT Software Solution
      • Flows
        • Flows
        • 3D-IC
        • Advanced Node
        • Arm-Based Designs
        • Library Characterization Flow
        • Low Power
        • Mixed Signal
    • Custom IC
      Custom IC / Analog/ RF Design Overview

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      Overview Related Products A-Z

      Product Categories
      • Circuit Design
        • Products
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • Circuit Simulation
        • Products
        • Spectre Simulation Platform
        • Spectre X Simulator
        • Spectre Accelerated Parallel Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • Layout Design
        • Products
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • Layout Verification
        • Products
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
        • Quantus Extraction Solution
        • Voltus-Fi Custom Power Integrity Solution
        • Tempus Timing Signoff Solution
      • Library Characterization
        • Products
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • Flows
        • Flows
        • Advanced Node
        • Electrically Aware Design
        • Legato Reliability Solution
        • Mixed Signal
        • Photonics
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
        • 5G Systems and Subsystems
    • Verification
      System Design and Verification Overview

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

      Product Categories
      • Debug Analysis
        • Products
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • Emulation
        • Products
        • Palladium Z1 Enterprise Emulation System
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • VirtualBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
      • Formal and Static Verification
        • Products
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
      • FPGA-Based Prototyping
        • Products
        • Protium S1 Desktop Prototyping Platform
        • Protium X1 Enterprise Prototyping Platform
        • SpeedBridge Adapters
      • Planning and Management
        • Products
        • vManager Metric-Driven Signoff Platform
      • Simulation and Testbench
        • Products
        • Xcelium Parallel Simulator
        • Incisive Functional Safety Simulator
        • Cadence Specman Elite
      • Software-Driven Verification
        • Products
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • Verification IP
        • Products
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP (VIP) Catalog
      • Flows
        • Flows
        • Verification Solution for ARM-Based Designs
        • Automotive Functional Safety
        • Metric-Driven Verification Signoff
        • Mixed-Signal Verification
        • Power-Aware Verification Methodology
    • IP
      IP Overview

      An open IP platform for you to customize your app-driven SoC design.

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      Product Categories
      • Interface IP
        • IP
        • PCI Express IP
        • CCIX IP
        • USB IP
        • SerDes IP
        • Ethernet IP
        • MIPI IP
        • HD Display IP
      • Denali Memory IP
        • IP
        • NAND Flash IP
        • DDR IP
        • HBM2 IP
        • SD / SDIO / eMMC IP
        • Octal and Quad SPI Flash Controller and PHY IP
      • Tensilica Processor IP
        • IP
        • HiFi DSPs for Audio, Voice, and Speech
        • ConnX DSPs for Radar, Lidar, and Communications
        • Vision DSPs for Imaging, Vision, and AI
        • Fusion DSPs for IoT
        • DNA Processor Family for On-Device AI
        • Tensilica Customizable Processors
        • Tensilica Reference Configuration
      • Analog IP
        • IP
        • Analog IP
      • System / Peripherals IP
        • IP
        • 8051 Microprocessor IP
        • System Bus Peripherals
        • Audio Controllers
      • Verification IP
        • IP
        • Accelerated VIP
        • Assertion-Based VIP
        • Memory Models
        • Simulation VIP
        • Productivity Tools
        • Interconnect Solution
    • IC Package
      IC Package Design and Analysis Overview

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      Overview Related Products A-Z

      Product Categories
      • IC Package Design
        • Products
        • Allegro Package Designer Plus
        • SiP Digital Architect
      • SI/PI Analysis Integrated Solution
        • Products
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI Analysis Point Tools
        • Products
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • Cross-Platform Co-Design and Analysis
        • Products
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • Flows
        • Flows
        • Cross-Substrate Interconnects
        • IC/Package/PCB Co-Design
        • InFO Packaging Technology
        • What's New in Sigrity Technology
        • Virtuoso System Design Platform
        • PDN Design
    • SYSTEM INNOVATION
    • System Analysis
      System Analysis Overview

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

      Product Categories
      • Electromagnetic Solutions
        • Products
        • Clarity 3D Solver
        • Sigrity XcitePI Extraction
        • Sigrity XtractIM
        • Sigrity PowerSI
      • Thermal Solutions
        • Products
        • Celsius Thermal Solver
      • Flows
    • Embedded Software
    • PCB Design
      PCB Design and Analysis Overview

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      Overview Related Products A-Z Service Bureaus PCB Resources

      Product Categories
      • Design Authoring
        • Products
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • PCB Layout
        • Products
        • Allegro PCB Designer
        • OrCAD PCB Designer
      • Library and Design Data Management
        • Products
        • Allegro ECAD-MCAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • Analog/Mixed-Signal Simulation
        • Products
        • Allegro PSpice System Designer
        • OrCAD PSpice Designer
      • SI/PI Analysis Integrated Solution
        • Products
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI Analysis Point Tools
        • Products
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • What's New in Allegro
        • Products
        • Board Layout
        • Schematic Capture
        • Data Management
      • What's New in Sigrity
        • Products
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • Flows
        • Flows
        • Multi-Board PCB System Design
        • Product Creation
        • ECAD/MCAD Co-Design
        • Allegro Right First-Time Design
        • IO-SSO Analysis Suite
        • 3D System Design Solutions
        • PDN Design
        • LPDDR4 Complete Solutions
        • Power Aware Signal Integrity Analysis
        • Interface-Aware Approach
        • Sigrity Serial Link Analysis
    • PERVASIVE INTELLIGENCE
    • AI IP Portfolio
    • AI / Machine Learning
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  • Solutions
    • INDUSTRIES
    • 5G Systems and Subsystems
    • Aerospace and Defense
    • Automotive
    • TECHNOLOGIES
    • 3D-IC Design
    • Advanced Node
    • Arm-Based Solutions
    • Cadence Cloud Portfolio
    • FPGA Development
    • Low Power
    • AI / Machine Learning
    • Mixed Signal
    • Photonics
  • Services
    • Services Overview

      Helping you meet your broader business goals.

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    • Design Services
    • Training
    • Methodology Services
    • Virtual Integrated Computer Aided Design (VCAD)
  • Support
    • Support
      Support Overview

      A global customer support infrastructure with around-the-clock help.

      More Cadence Online Support Portal

      • Support Process
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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      • Computing Platform Support
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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      • Customer Support Contacts
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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    • TRAINING COURSES
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Advanced Nodes (ICADV)
        • Featured Courses
        • Virtuoso Layout for Advanced Nodes
        • Virtuoso Layout for Advanced Nodes: T1 Place and Route
        • Virtuoso Layout for Advanced Nodes: T2 Electromigration
      • Circuit Design and Simulation
        • Featured Courses
        • Virtuoso ADE Assembler Series
        • Virtuoso ADE Verifier
        • Design Checks and Asserts
        • Mixed-Signal IP and Testbench Reuse
        • Mixed-Signal Simulations Using Spectre AMS Designer
        • Spectre Accelerated Parallel Simulator
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
        • Additional Courses
      • Electrically-Aware Design
        • Featured Courses
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
        • Physical Verification System
        • Virtuoso Analog Design Environment
        • Virtuoso Electrically-Aware Design with Layout-Dependent Effects
        • Virtuoso Schematic Editor
        • Quantus Extraction Solution Series
        • Spectre Accelerated Parallel Simulator
      • Infrastructure
        • Featured Courses
        • Advanced SKILL Language Programming
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming
        • SKILL Language Programming Fundamentals
        • SKILL Language Programming Introduction
        • SKILL Programming for IC Layout Design
      • Layout Design and Verification
        • Featured Courses
        • Virtuoso Layout for Advanced Nodes
        • Virtuoso Layout Pro Series
        • Virtuoso Space-Based Router
        • Virtuoso Floorplanner
        • Virtuoso Abstract Generator
        • Physical Verification Language Rules Writer
        • Virtuoso Connectivity-Driven Layout Transition
        • Virtuoso Layout Design Basics
        • Physical Verification System
        • Quantus Extraction Solution Series
      • Library Characterization
        • Featured Courses
        • Cadence Library Characterization and Validation
        • Virtuoso Liberate MX for Memory Characterization
        • Cadence Variety Statistical Library Characterization
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
        • Spectre Accelerated Parallel Simulator
        • Virtuoso ADE Assembler Series
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Mixed-Signal Simulations Using Spectre AMS Designer
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
        • Mixed-Signal IP and Testbench Reuse
        • Virtuoso ADE Explorer Series
      • RF Design
        • Featured Courses
        • Quantus QRC Transistor-Level T1: Overview and Technology Setup
        • Quantus QRC Transistor-Level T2: Parasitic Extraction
        • Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
        • Spectre RF Analysis Using Shooting Newton Method
        • Spectre RF Analysis using Harmonic Balance
        • Spectre Simulator Fundamentals Series
        • Virtuoso ADE Explorer Series
      • Variation Aware Design
        • Featured Courses
        • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
        • Virtuoso ADE Assembler S2: Sweeping Variables, Simulating Corners, and Creating Run Plans
        • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Spectre Pro Series
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Languages and Methodologies
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Assertions
        • Featured Courses
        • SystemVerilog Assertions
        • Verification with PSL
      • Behavioral Language for AMS Simulation
        • Featured Courses
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
      • High-Speed PCB Design
        • Featured Courses
        • Essential High-speed PCB Design for Signal Integrity
        • PCB Design at RF - multi-Gigabit Transmission, EMI Control, and PCB Materials
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Verification
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Synthesis with Stratus HLS
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SVA, Formal and JasperGold Fundamentals for Designers
        • SystemVerilog Accelerated Verification with UVM
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog Assertions
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog Language and Application
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Digital Design and Signoff
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Implementation
        • Featured Courses
        • Analog-on-Top Mixed-Signal Implementation
        • Innovus Implementation System (Block)
        • Innovus Implementation System (Hierarchical)
        • Virtuoso Digital Implementation
      • Equivalence Checking
        • Featured Courses
        • Conformal Low-Power Verification
        • Conformal ECO
        • Conformal Equivalence Checking
      • Silicon Signoff
        • Featured Courses
        • Basic Static Timing Analysis
        • Tempus Signoff Timing Analysis and Closure
        • Voltus Power-Grid Analysis and Signoff
      • Synthesis and Test
        • Featured Courses
        • Advanced Synthesis with Genus Stylus Common UI
        • Advanced Synthesis with Genus Synthesis Solution
        • Fundamentals of IEEE 1801 Low-Power Specification Format
        • Genus Synthesis Solution
        • Genus Synthesis Solution with Stylus Common UI
        • Joules Power Calculator
        • Low-Power Synthesis Flow with Genus Stylus Common UI
        • Low-Power Synthesis Flow with Genus Synthesis Solution
        • Test Synthesis Using Genus Synthesis Solution
        • Test Synthesis with Genus Stylus Comon UI
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Cross-Platform Co-Design and Analysis
        • Featured Courses
        • OrbitIO System Planner
        • SiP Layout
      • IC Package Design
        • Featured Courses
        • Allegro Package Designer
        • SiP Layout
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
        • Allegro Sigrity PI
        • Allegro Sigrity Package Assessment and Model Extraction
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
        • Allegro Sigrity Package Assessment and Model Extraction
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • PCB Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Analog/Mixed-Signal Simulation
        • Featured Courses
        • Advanced PSpice for Power Users
        • Allegro AMS Simulator
        • Allegro AMS Simulator Advanced Analysis
        • Analog Simulation with PSpice
        • Analog Simulation with Pspice Advanced Analysis
      • Design Authoring
        • Featured Courses
        • Allegro System Design Authoring
        • Allegro Design Entry HDL Basics
        • Allegro Design Entry HDL Front-to-Back Flow
        • Allegro Design Entry HDL SKILL Programming Language
        • Allegro Design Entry Using OrCAD Capture
        • Allegro Design Reuse
        • Allegro System Architect
        • Allegro Team Design Authoring
      • Library and Design Data Management
        • Featured Courses
        • Allegro Design Workbench for Administrators
        • Allegro Design Workbench for Engineers and Designers
        • Allegro Design Workbench for Librarians
        • Allegro PCB Librarian
      • PCB Layout
        • Featured Courses
        • Allegro Update Training
        • Allegro High-Speed Constraint Management
        • Allegro PCB Editor Basic Techniques
        • Allegro PCB Editor Intermediate Techniques
        • Allegro PCB Editor SKILL Programming Language
        • Allegro PCB Router Basics
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity SI Foundations
        • Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM​
        • Sigrity PowerDC and OptimizePI
        • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
        • Sigrity PowerDC and OptimizePI
        • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Emulation and Acceleration
        • Featured Courses
        • Acceleration with Palladium XP
        • Protium Rapid Prototyping Platform
      • Formal Verification
        • Featured Courses
        • SVA, Formal and JasperGold Fundamentals for Designers
        • SystemVerilog Assertions
        • Verification with PSL
      • Planning and Management
        • Featured Courses
        • Foundations of Metric Driven Verification
        • Metric Driven Verification Using Incisive vManager
        • vManager Tool Usage in Batch Mode
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Simulation, Testbench and Debug
        • Featured Courses
        • Incisive Functional Safety Simulator
        • Incisive Simulation Performance Optimization
        • Indago Debug Analyzer App
        • Low-Power Simulation with IEEE Std 1801 UPF
        • Xcelium Simulator
        • Xcelium Integrated Coverage
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Synthesis with Stratus HLS
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Verification
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SVA, Formal and JasperGold Fundamentals for Designers
        • SystemVerilog Accelerated Verification with UVM
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog Assertions
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verification IP
        • Featured Courses
        • VIP Basic Building Blocks and Usage
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog Language and Application
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Tensilica Processor IP
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • ConnX DSPs
        • Featured Courses
        • Tensilica ConnX B10 DSP
        • Tensilica ConnX B20 DSP
        • Tensilica ConnX BBE16EP Baseband Engine
        • Tensilica ConnX BBE32EP Baseband Engine
        • Tensilica ConnX BBE64EP Baseband Engine
      • Fusion DSPs
        • Featured Courses
        • Tensilica Fusion F1 DSP
        • Tensilica Fusion G3 DSP
        • Tensilica Fusion G6 DSP
      • HiFi DSPs
        • Featured Courses
        • Tensilica HiFi 2/EP/Mini Audio Engine ISA
        • Tensilica HiFi 3 Audio Engine ISA
        • Tensilica HiFi 4 DSP
        • Tensilica HiFi 5 DSP
      • Tensilica Processors
        • Featured Courses
        • Tensilica Instruction Extension Language and Design
        • Tensilica Xtensa LX Processor Fundamentals
        • Tensilica System Modeling using XTSC
        • Tensilica Xtensa LX Hardware Verification and EDA
        • Tensilica Xtensa LX Processor Interfaces
        • Tensilica Xtensa NX Hardware Verification and EDA
        • Tensilica Xtensa NX Processor Fundamentals
        • Tensilica Xtensa NX Processor Interfaces
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  • Palladium Z1 Enterprise Emulation Platform

Palladium Z1 Enterprise Emulation Platform

Supports global design teams with fast emulation throughput and optimal workload efficiency

Palladium Z1 Enterprise Emulation Platform Datasheet

Emulation Throughput White Paper

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Key Benefits

  • Enterprise-level reliability and scalability, with 5X greater emulation throughput
  • Better resource utilization via advanced virtual target relocation and job re-shaping capabilities
  • 92% smaller footprint via rack-based blade architecture
  • Secure, scalable, and on-demand access with Palladium Cloud

Verification has become the biggest challenge in SoC development. However, traditional verification tools haven’t kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle. 

As the industry's first datacenter-class emulation system, the Palladium® Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.

Compared to the previous generation, the platform, which brings together simulation acceleration and emulation technologies, delivers up to 5X better emulation throughput and, on average, 2.5X better workload efficiency than the closest competitor. 

Palladium Z1
Easy to manage and scale, the platform:
  • Compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation
  • Allocates as many workloads as possible
  • Runs workloads based on priorities
  • Debugs for both pre- and post-silicon bugs

Smart Emulation Resource Utilization

The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform’s unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with 4 million gate granularity and scales to 9.2 billion gates. 

Compared to the Palladium XP II environment, the new platform offers an up to 44% reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more. The power advantages are a result of:

  • An average of 2.5X better system utilization and number of parallel users
  • Up to 5X better emulation throughput
  • Up to 140MG per hour compile times
  • Superior debug depth and upload speeds

Its rack-based blade architecture results in a 92% smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering 4X better user granularity than its nearest competitor.

Through a compile flow, the Palladium Z1 platform is congruent with the Protium S1 FPGA-Based Prototyping Platform and the Protium X1 Enterprise Prototyping Platform for software development, system validation, and hardware regressions.

Features

  • Processor-based compute engine and Verification Xccelerator Emulator (VXE) software deliver up to 2X faster compiles, run higher performance verification, and support flexible new use models
  • Virtual Verification Machine (VVM) supports interactive offline debug
  • Cadence Xcelium® simulator users can hot-swap from simulation to acceleration without recompilation
  • Enables quick bring-up via fast, automated, intelligent compiler
  • Facilitates quick system-level bring-up with comprehensive Cadence SpeedBridge® Adapter portfolio and Accelerated Verification IP
  • Enables dynamic power analysis and verification via interoperability with the Cadence Joules™ RTL Power Solution
  • Supports pre-qualified and configured Emulation Development Kit (EDK) portfolio for USB and PCI Express® for rapid driver development and design verification
  • Supports coverage and metric-driven verification
  • Features hybrid environment for early hardware/software validation of design and embedded testbenches for comprehensive verification and re-use methodology
  • Provides high-level synthesis with Cadence Stratus™ High-Level Synthesis (HLS), so you can integrate high-level abstraction models into the system verification environment
  • Supports case-based verification with Cadence Perspec™ System Verifier for SoCs that reduces complex system-level coverage-driven test development time

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TRAINING COURSES

Smart JasperGold
Formal Verification

Third-generation platform
leveraging machine learning
technology

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Verification Suite

Reduce system integration
time by up to 50%

GET DETAILS

Protium S1 Platform

Reduce FPGA-based prototype
bring-up from months to days

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Palladium Z1 Design Team —

Winner of UBM's 2016 ACE Award

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Emulating NVIDIA GPUs with Cadence Emulation Products

  • Related Products

    • Cadence Verification Suite
    • Palladium Hybrid
    • Palladium Dynamic Power Analysis
    • Protium S1 Desktop Prototyping Platform
    • Protium X1 Enterprise Prototyping Platform
    • SpeedBridge Adapters
    • Incisive Enterprise Simulator
    • VirtualBridge Adapters
Resource Library VIEW ALL

Press Releases (17)

  • Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
  • Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
  • Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
  • Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
  • Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
  • Cadence Announces Next-Generation JasperGold Formal Verification Platform
  • Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
  • M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
  • DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
  • Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
  • Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
  • CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
  • HiSilicon Expands Cadence Palladium XP Platform Usage For Mobile and Digital Media SoC and ASIC Development
  • Cadence Redefines Verification Planning and Management with Incisive vManager Solution
  • Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development

Video (14)

  • Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory
  • The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
  • Using the Cadence VirtualBridge Emulator with the Palladium Platform
  • Taking FPGA-Based Prototyping to the Next Level
  • Palladium Z1: Advanced Job Re-shaping
  • Emulating Nvidia GPUs
  • NVIDIA Handles Complexity with Palladium Z1 Platform
  • Verify Smarter with Industry's First Datacenter-Class Emulation System
  • Pre and Post Silicon Verification: The Best of Both Worlds
  • Using Palladium Platform to Exhaustively Verify a Configurable Coherent NoC IP
  • Delivering High Quality Denver IP Utilizing IP Acceleration
  • Introducing the Palladium Z1 Enterprise Emulation Platform
  • National and Cadence Building a More Efficient Chip Design Flow
  • A Look at Cadence System Development Tools

White Paper (2)

  • Improving Emulation Throughput for Multi-Project SoC Designs White Paper
  • A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper

Datasheet (15)

  • Memory Model Portfolio for Palladium Series Datasheet
  • VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
  • Virtual JTAG Virtual JTAG Debug Interface Datasheet
  • Emulation Development Kit for Palladium Series Datasheet
  • Palladium Z1 Enterprise Emulation Platform Datasheet
  • Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
  • Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
  • Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
  • SpeedBridge Adapter for USB 3.0 Devices Datasheet
  • Cadence SpeedBridge Adapter for Ethernet Datasheet
  • Cadence Accelerated Verification IP for PCI Express Datasheet
  • Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
  • Cadence Incisive SpeedBridge Adapter for PCI Express 2.0 Datasheet
  • Cadence SpeedBridge Adapter for PCI Express Datasheet

Success Story Video (2)

  • NVIDIA Handles Complexity with Palladium Z1 Platform
  • Introducing the Palladium Z1 Enterprise Emulation Platform

Customers Success (1)

  • Renesas Deploys Cadence Interconnect Workbench with Palladium Z1 Platform
Videos

A Look at Cadence System Development Tools

Augmenting Simulation Via Low-Power Verification Methodologies with Emulation

Verification Solutions for ARM v7/v8 Based Systems on Chip

Using the Cadence VirtualBridge Emulator with the Palladium Platform

Palladium Z1: Advanced Job Re-shaping

Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory

News ReleasesVIEW ALL
  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

  • Cadence Delivers Portable Test and Stimulus Methodology and Library 07/17/2019

  • Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development 06/19/2019

  • Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development 05/28/2019

  • NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs 05/28/2019

BlogsVIEW ALL
Customers

Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.

Narenda Konda, Director of Engineering, NVIDIA

Read More or View All Customers

The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.

Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei

Read More or View All Customers

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