Cadence® AWR Design Environment® Version 15 (V15) offers new and enhanced technologies that provide greater design efficiency and first-pass success to engineering teams developing or integrating III-V ICs, multi-technology modules, and PCB assemblies for 5G, automotive, and aerospace/defense applications. Engineering productivity is improved with new analyses, faster and higher capacity simulation technologies, time-saving design automation, and 5G New Radio (NR)-compliant testbenches that support power amplifier (PA) and antenna/array design, electromagnetic (EM) modeling, and RF/microwave integration across heterogenous technologies.
Deliver spurious-free, high-performance PAs with new stability analysis, video-band load pull, and enhanced simulation technologies
Solve complex structures faster using EM analysis with enhanced meshing and smart geometry handling for chip, package, and board characterization
Ensure wireless products are ready for 5G NR with preconfigured, standards-compliant testbenches addressing mobile device and infrastructure applications
Circuit Design and Simulation
Develop oscillation-free PAs with fast, rigorous stability analysis/optimization
Perform rigorous stability analysis for multistage amplifiers and transistors connected in parallel with far fewer computations. The significantly faster simulation time makes this new technique ideally suited for optimizing stabilization networks.
Reduce IMD with advanced load-pull analysis
Minimize intermodulation distortion (IMD) of wideband amplifiers using optimal low-frequency (F1-F2) source/load impedances derived from two-tone load-pull simulations. (See demo)
Design-in-place with integrated transmission-line calculator/synthesis
Calculate and set transmission line dimensions directly from a schematic for a specified impedance and electrical length directly from the microstrip, stripline, coplanar or rectangular waveguide, or coaxial components, accelerating the design of distributed networks such as Wilkinson dividers, branchline couplers, and quarter-wave transformers. (See demo)
Synthesize antenna, MMIC and PCB matching circuits with PDK/vendor components
Address challenging antenna, wideband and multi-band PAs, and inter-stage impedance matching design using networks synthesized with components from the Cadence AWR Microwave Office® vendor library and foundry-authorized process design kits (PDKs). (See demo)
Analyze EM structures faster with more intelligent adaptive meshing
The Cadence AWR AXIEM® 3D planar EM analysis's meshing and solver technology improvements provide faster, more robust EM analysis with the ability to detect and fix problematic mesh facets automatically, and to address manufacturing details that do not impact electrical behavior. (See demo)
Optimize and plot performance with peak antenna measurements
Antenna radiation pattern peaks for E-Phi, E-Theta, E-LHCP, E-RHCP, and total radiate power can now be plotted and optimized as a function of swept frequency directly from measurement and optimization dialog boxes. (See demo)
System Simulation and Models/Libraries
Evaluate designs with preconfigured 5G NR testbenches/libraries
New testbenches accelerate component design and evaluation processes with preconfigured 5G NR TX and RX blocks and measurements. The 5G NR library contains TX/RX functionality for DL/UL modes, supporting FR1 and FR2 frequency bands and test models for DL signal source and receiver configurations.
Manage multiplexed signals with phased array MIMO bus support
The phased array model block operating in multiple-in-multiple-out (MIMO) mode now supports buses on the circuit and radiated sides of the array assembly, offering more comprehensive RF modeling of multiplexed signals.
Investigate PA linearization with DPD
The new digital predistortion (DPD) block offers algorithms to linearize nonlinear amplifiers. The new DPD model supports memory polynomial, generalized memory polynomial, dynamic deviation reduction of second order (DDR2), and lookup tables.
Design Environment, Layout, and Automation
Integrate diverse technologies with mixed physical units/grid
Hierarchical designs now support mixed physical units for chip, package, and board subcircuits using different layout process definitions.
Minimize physical footprints with DRC compliant iNets routing
Place and route intelligent nets (iNets) as closely as possible without violating design rule check (DRC) separation rules using dynamically calculated, minimum spacing routing guides.
Visualize load-pull contours with rectangular plots
Smith chart or polar plot measurements can now be plotted on a rectangular grid with independent axis control, allowing designers to more easily identify impedances associated with peak performance from load-pull contours. (See demo)
Compare different network combinations with template-based measurements
A single measurement on a parent document containing subcircuit templates can expand to individual measurements for all permutations, enabling users to quickly set up testbenches and compare combinations of networks.