Flexible
The PHY IP is easily configurable to meet application needs for multi-link use cases, support for Ethernet and PCIe protocols makes it versatile for most common applications in the HPC space
Power Efficient
Cadence PHY IP for PCIe and CXL is designed to provide best-in-class power efficiency for the latest PCIe standards while meeting data and clock recovery requirements in high-speed, high-dB-loss, and high-crosstalk channels
Designed for the Future
The PHY IP is available in advanced FinFET process nodes and designed for the most challenging low-latency applications made possible by newer versions of the PCIe 7.0, 6.0, and 5.0 and CXL standards
PCIe 5.0 Sub-system Silicon Demo
Cadence demonstrates the IP industry’s first full 8-lane PCIe 5.0 sub-system solution on a single chip. The subsystem consists of Cadence’s latest PCIe 5.0 PHY and controller technology interoperating at 32GT/s with leading OEM server platform and test equipment vendors. The subsystem solution is available in 7,6,5, and 3nm process nodes with scalability to support up to 16-lane configurations.
