The Cadence HBM3e Solution at 12.4Gbps
This video shows a demo of the Cadence HBM3e solution, performance, and robustness of the eye at 12.4Gbps and reads/writes to the HBM3 stack at the DRAM speed.
Overview
The Cadence High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require the highest-bandwidth, low-latency memory solution. The memory subsystem PHY supports data rates up to 8.4Gbps per data pin, featuring 16 independent channels, for a total data width of 1024 bits. The PHY is designed for a 2.5D system with a silicon interposer to route signals between the 3D DRAM stack and PHY. The third-generation design is optimized for low power consumption and low PHY area. Cadence provides the complete solution including PHY, interposer, and package.
Key Benefits
Highest Performance
HBM3E up to 8.4Gbps per pin and HBM2E up to 3.6Gbps per pin
Low Latency
For data-intensive applications
Low Power and Area
Low-power control and advanced low-power modes with power down
Easy integration
PHY is hardened, and timing closed including all I/O and decoupling capacitors
Complete HBM Solution
Full system design including PHY, interposer, and package
Excellent Support
Access to Cadence expert SI/PI team to support customer designs