Overview
Cadence® Denali® solutions offer world-class DDR/LPDDR PHY and controller memory IP that is extremely flexible and can be configured to support a wide range of applications and protocols.
Cadence supports your SoC/IP integration and development with EDA tools, Palladium® emulation, SystemC® TLM models, Verification IP (VIP), and Rapid System Bring-Up software.
Key Benefits
Multi-protocol Solution
DDR and LPDDR supported in a single IP
Highly Configurable
Application-specific parameters and floorplan optimization
Low Latency
For data-intensive applications
Low Power and Area
Industry-leading PPA based on advanced architecture and implementation
Reliable
Maximum system margin with advanced clocking and I/O architectures
Future proof
Cutting edge technology with the latest memory protocols and the highest data rates
Products
Full IP Integration Solutions
Rapid System Bring-Up
With other solutions, system bring-up is gated by the need for customers to write their own firmware U-Boot code in order for the SoC’s CPU to boot DRAM. This can result in the long-awaited first silicon sitting in the lab for days or weeks—after all, nothing works until the DRAM works.
However, with the Cadence Rapid System Bring-Up software, users can:
- Directly access DRAM controller and PHY registers through JTAG
- Bring up DRAM interface fast—typically in one day
- Use software that allows 2D eye shmoo on any pin—without probing
- Easily port DRAM parameters into chip-level firmware
- Allow Cadence staff to remotely and securely debug DRAM interface issues
We use Cadence LPDDR4 IP in our fast turnaround video solution for digital video consumer applications, such as cameras and TVs. We succeeded in bringing up our LPDDR4 memory subsystem with the help of Cadence DDR IP bring-up software within an hour of receiving the chip back.
– Japanese SoC vendor
We used the DDR IP bring-up software to try various IP settings and determine the optimal DDR system initialization code to be used in the firmware.
– US-based system OEM
We used Cadence bring-up software enabled on windows laptop and were able to perform training and BIST to successfully write/read/compare DDR memory. Pretty good success for just over an hour of work.
– US-based storage OEM
Emulation Models
To undertake comprehensive system-level SoC/ASIC verification, you need to stress and validate your design in a scalable verification environment—one that offers a high degree of control and visibility, applies system-level stimulus to the design, and verifies the performance and behavior of the integrated system. Using Cadence® high-throughput emulation technology, design and verification teams can rapidly bring-up, verify, debug, and turn around their hardware and software designs using realistic system-level environments.
TLM Models
Cadence Transaction Level Models (TLM) are available in Incisive/Xcelium and Accellera SystemC.
Two distinct types of TLM models offered are approximately timed (AT) and loosely timed (LT) models.
Both types of TLM models are offered for Cadence memory IP.
AT models are suitable for architectural exploration and performance benchmarking.
LT models are used for increased regression performance and verification throughput for system analysis and verification.
