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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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        • Low Power
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        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
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        • Low Power
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      • Industries
        • 5G Systems and Subsystems
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        • Hyperscale Computing
      • Technologies
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Rigid-Flex

Minimize iterations for Rigid-Flex designs

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Rigid-Flex PCBs comprised of rigid and flexible substrates laminated together are inside a variety of small electronic products. Flexible PCBs (flex/Rigid-Flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. The Cadence® Allegro® and OrCAD® 17.2-2016 release enables several new capabilities that minimize design iterations and lower overall cost for flex and Rigid-Flex designs commonly used in automotive, consumer electronics, computing, communications, mobile, and wearable applications.

Key flex and Rigid-Flex features in the release include:
Stack-Up by Zone for Flex and Rigid-Flex Designs

Multiple zones can be created using the new Cross-Section Editor to represent Rigid-Flex/rigid PCBs. A physical zone is used to map an area of the design to one of the stack-ups created in the Cross-Section Editor. Zones automatically include associated keepouts and optional constraint regions and rooms. In-design rules coupled with this enhanced definition ensure that the design is correct by construction. An accurate definition of Rigid-Flex/rigid design can also be passed on to MCAD systems using IDX data exchange, eliminating unnecessary MCAD-ECAD iterations.

Allegro 17.2 - 2016 Release
In-Design Inter-Layer Checks for Rigid-Flex Design

The number of conductive and non-conductive layers on flex and Rigid-Flex designs are increasing as the fabrication industry innovates to meet customer needs. This explosion of different types of materials and associated rules that are imposed on designers is increasing the amount of work PCB designers have to do to leverage the advances in Rigid-Flex technology.

New in-design inter-layer checks in the Allegro PCB Editor provide the ability to check geometries between two different layers. In typical PCB designs, various masks and surface finishes require verification of proper clearances and coverage. Rigid-Flex designs not only have the same mask and surface finish requirements, but also the addition of bend areas, stiffeners, and so on, which require special clearances or overlaps of materials, spacing, and design features. These objects that are represented on different subclasses require verification between these layers, and this capability is now supported using the inter-layer checks capabilities.

The inter-layer checks capability is a new design rule check (DRC) engine designed to check mask layer to mask layer geometry, as well as mask layer to surface metal. It allows checks for:

  • Coverlay to pad
  • Mask to pad
  • Precious metal to coverlay
  • Bend area/line to stiffener, component, pin, and via

 

 

Allegro PCB Editor 17.2

The release introduces 12 new layers and 19 new surface finishes and allows users to enable checks against these layers using user-defined clearances or user-specified overlaps. Once enabled, the checks provide feedback during the layout process to avoid design-verify-redesign iterations. 

Image showing Allegro Rigid-Flex Manager and how to set spacing
Enhanced Contour, Arc-Aware Routing

Enhanced Contour is a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. This feature has been improved over the legacy contour feature by removing a continuous dialog popup, introducing a simple canvas-based two-state click use model and enabling shove of existing connect lines. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners.

Related Links

  • Why Move Up to Allegro 17.2-2016? So How Does Your Design “Stack-Up”?
  • Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support 

Contact Us

TRAINING COURSES

Learn how a stack-up-by-zone feature provides faster, easier definition of stack-ups and improved MCAD-ECAD co-design while in-design inter-layer checking technology minimizes design-check-redesign iterations for flex and Rigid-Flex design

Avoid Costly Fabrication Errors with Real-Time Inter-Layer Checks Webinar

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Resource Library

Press Releases (4)

  • Cadence and Dassault Systèmes Partner to Transform Electronic Systems Development | Cadence
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard | Cadence
  • New Cadence Allegro Platform Accelerates Design of Compact, High-Performance Products Using Flex and Rigid-Flex Technologies | Cadence
  • Cadence Strengthens Allegro Technology Portfolio to Make Design Cycles Shorter and More Predictable | Cadence

Datasheet (1)

  • Allegro PCB Design Solution Datasheet

Webinar (2)

  • Conquer High-Speed Interfaces Faster
  • Gain an Unfair Advantage - Make Better Products Faster with Cadence PCB Tools

White Paper (1)

  • Automating Inter-Layer In-Design Checks in Rigid-Flex PCBs White Paper
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Videos

Accelerating PCB Design Cycles with In-Design Analysis

CadenceLIVE Taiwan: Rigid-Flex PCB Design and EM Analysis Using a Front-to-Back Cadence Flow

Rigid-Flex PCB Design and EM Analysis Using a Front-to-Back Cadence Flow

CadenceLIVE Taiwan: RF to mmWave Front-End Component Design for 5G NR

Allegro PCB Symphony Team Design 17.2 Release

Team Source Your PCB Layout - Hassle Free Real-Time Team Design

News ReleasesVIEW ALL
  • Cadence and Dassault Systèmes Partner to Transform Electronic Systems Development 02/22/2022

  • New Cadence Allegro X Design Platform Revolutionizes System Design 06/08/2021

  • Cadence Unveils Next-Generation Sigrity X for Up to 10X Faster System Analysis 03/16/2021

  • Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers 12/02/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

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