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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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What's New in Sigrity Technology 2016

New products, updated features, and purchasing options

  • What's New in Sigrity
  • Sigrity 2017
  • Sigrity 2016
  • Sigrity 2015

Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces

Cadence expanded its Sigrity™ technology portfolio with new products and capabilities:

  • Upgraded serial link analysis flow to accelerate the time to pass compliance tests
    • New IBIS-AMI model building technology takes industry-proven equalization algorithms and provides a wizard-based graphical interface to rapidly facilitate creation of IBIS-AMI models. Available in two tiers, one that enables creation of models strictly for Sigrity tools, and another that creates models suitable for any IBIS-AMI compliant simulator.
    • New cut-and-stitch model extraction technology allows for segmenting long serial links into sections that should be modeled using 3D full-wave and sections that can be modeled using hybrid extraction technology. The resultant model is extracted 10X faster than a strictly 3D full-wave extraction with 95% accuracy.
    • New USB 3.1 (Gen 2) compliance kit to confirm that the 10Gbps interface requirements are met.
      • Sigrity SystemSI™ technology
      • Sigrity PowerSI® technology
      • Sigrity PowerSI 3D EM Extraction Option
  • Optimized design flow between PCB designer and power integrity engineer
    • New cross-probing between DC analysis report file and Allegro® editing canvas
    • Batch DC analysis available directly from the Allegro editing canvas
    • Review previously generated DC analysis report files from the Allegro editing canvas
      • Sigrity PI Base
      • Sigrity PowerDC™ technology
  • Optimized design flow between IC package designer and characterization engineer
    • Batch electrical performance assessment (EPA) available directly from the IC package designer’s editing canvas
    • Batch package model creation using hybrid solver technology directly from the IC package designer’s editing canvas
    • Review previously generated EPA report data from the IC package designer’s editing canvas
      • Sigrity XtractIM™ technology
  • Upgraded 3D interconnect modeling to enable rapid modeling of low-cost PCB and IC packages
    • New rapid and accurate capacitance extraction technology
    • Quickly produce RLCG interconnect models for designs with few (or no) power and ground planes/shapes using new 3D quasi-static extraction technology
      • Sigrity PowerSI 3D EM Extraction Option
DesignCon 2016: Sigrity 2016 Portfolio Highlights

Ken Willis, Cadence product engineering director, discusses the company's DesignCon 2016 highlights ranging from serial link analysis and DDR/LPDDR support to the Sigrity 2016 portfolio's new products and enhancements including generating AMI models and a quasi-static field solver.

Watch video

TRAINING COURSES

Videos

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

SiriusXM Simulates DDR3 Interfaces with Sigrity Tools

Nexus Interposers and Cadence Tools Enhance DDRx Designs

News ReleasesVIEW ALL
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

Blogs VIEW ALL

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