This growing library of informational videos will give you helpful tips on how to use Cadence® Sigrity™ tools to accomplish important signal integrity (SI)- and power integrity (PI)-related tasks. While these videos are meant to explain “how to” for the tool user, they also spend a little time on why each particular task is important in the overall design methodology.
How to Resolve Common IC Package Electrical Concerns
Sigrity technologists guide you step by step on how IC package designers can conveniently identify electrical problems throughout the design cycle. Following this methodology, experts are enabled to focus on the difficult problems without getting overloaded and design cycles times are reduced. Allegro Package Designer and Sigrity XtractIM technology from Cadence are demonstrated.
How to Build Accurate Leadframe Package Models Quickly and Easily
Sigrity technologists guide you step by step on how to set up a leadframe package design for accurate extraction using the 3D quasi-static solver engine. Accurate RLC extraction is performed on a leadframe design from the same environment used to model multi-layer packages with other solver engines. Design productivity is improved by enabling a common environment to model leadframe, flip-chip, and wirebond IC packages. Allegro Sigrity SI Base and the Allegro Sigrity Package Assessment and Extraction Option are demonstrated.
How to Simulate the Impact of ESD and Determine How Many TVS Diodes are Necessary
Learn how to apply an ESD gun model to simulate an ESD event on a printed circuit board. Learn how passive components such as transient-voltage-suppression (TVS) diodes can protect your design from an ESD event without overdesigning the protection scheme. By utilizing the ESD simulation workflow early in the design cycle, you will bring your cost-effective prototype to the lab with confidence you can avoid time consuming lab debug and re-design because of unveiled ESD issues. Cadence Sigrity SPEED2000 is demonstrated.
How PCB Designers Can Jumpstart Electrical Signoff Using Power-Aware Rule Checks
Sigrity technologists guide you step by step on how to utilize power-aware electric rule checks to confidently fast track the signoff process for your PCB designs.
How to Find Signal Integrity Problems on an Unrouted PCB
Sigrity technologists guide you to discover many signal integrity problems as soon as a PCB design has been placed. The methodology enables finding and fixing many signal integrity concerns without having to rip up and re-route a design. Learn about Sigrity Aurora and the new flow planning feature for route planning with signal integrity analysis through a brief demonstration.
How PCB Designers Can Create Initial PDN Constraints Without Becoming a PI Expert
Learn how to setup your power delivery network constraints by using straight-forward IPC calculations. PCB designers can quickly develop/verify their design. In addition, view demos of Allegro Sigrity PI Base and PI Signoff and Optimization option.
How PCB Designers Can Find and Fix Power Integrity Problems
Learn how PCB designers can solve basic PI problems. This video will guide you step by step, how to place effective decoupling capacitors, perform DC analysis using the Sigrity PowerDC engine. Learn about Allegro Sigrity PI Base (http://goo.gl/k7XCaG)
How PCB Design Teams Can Perform IR Drop Analysis Early and Often
Learn how to automatically set-up PDN simulation from schematics, collect, verify component models, perform analysis as early as possible in the design process. In addition, download the white paper to learn how a front-to-back, collaborative team-based approach to PCB power integrity analysis works: https://goo.gl/GaFpy7
How to Share Power Delivery Network Design Analysis Across the PCB Design Team
Learn step by step from Sigrity experts how to automatically set up PDN simulation from schematics as well as collect and verify component models. The video demonstrates Allegro Sigrity PI Base (http://goo.gl/k7XCaG) and the PI Signoff and Optimization option (https://goo.gl/3AOH2r) from Cadence
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