Key Benefits
- Innovative environment with smart target technology
- Accelerates timing closure by 4X
- Solves timing closure challenge
Cadence® Allegro® TimingVision™ technology provides an innovative and unique environment that allows you to see real-time delay and phase information right on the routing canvas.
As data rates increase and supply voltages decrease in today’s high-performance interfaces (i.e. DDR3/DDR4, PCle® Gen3 and SATA), PCB and IC package designers have to spend more time to ensure that signals in an interface meet timing requirements. With increasing density, the effort to get to timing closure—ensuring all signals meet timing requirements—can increase significantly. Layout designers need new tools to meet this increasingly complex challenge.
With the embedded route engine, the Allegro TimingVision environment provides real-time feedback during interactive editing and enhances your ability to develop a strategy for resolving timing on large buses or interfaces such as DDRx and PCIe. Coupled with Auto-interactive Phase Tuning (AiPT) and Auto-interactive Delay Tuning (AiDT) capabilities, this environment lets you speed timing closure of high-speed PCB interfaces by up to 75%.
AiDT
Auto-interactive Delay Tuning (AiDT) automatically generates tuning patterns on a user-selected routed byte lane or interface based on user-defined timing constraints and tuning parameters. AiDT computes the required length for the connections to meet timing constraints, and utilizes controlled push/shove techniques when adding tuning patterns.
AiPT
Auto-interactive Phase Tuning (AiPT) automatically matches dynamic and static phases for the selected differential pairs. It works with a set of parameters that provides you with several options for trace lengthening or shortening as well as pad entry/exit options. With AiPT, you can significantly shorten the time to match static and dynamic phases for differential pairs
