Allegro Front-End Design

What’s New in Allegro Design Authoring

Support for Watermark in the Generated PDF File

With the Cadence^® Allegro^® 17.2-2016 release, users can now embed a watermark in the generated PDF file. A watermark can either be text or an image placed as a background on all the pages of the PDF file. For example, text such as “First Prototype”, “Confidential”, or “Review Copy” can be added as a watermark. Similarly, the company’s logo is an example of an image as a watermark. Using a watermark on the generated schematic PDF file is optional. You have the option to use it only while viewing the PDF file, only when printing the file, for both viewing and printing, or not at all.

Tag-Based ECSet Mapping

ECSet nodes now support tags (pin parameter) that can be used to uniquely identify a pin and remove any ambiguity. They can be used to lock the mapping between the ECSet and associated nets, and will not be impacted by the placement or the RefDes changes.

Tags can be defined in a design prior to ECSet extraction or ECSet application in Constraint Manager, and can also be defined in SigXplorer. Tags can be added to pins in a design prior to extracting a topology into SigXplorer. The tags can be used to schedule a topology and to apply the topology back to the design.

Port Groups

Nets that have similar functionality can be grouped together to create a Net Group. Net Groups help in managing the nets as a single object and provide a higher level of abstraction for the design purposes. Net Groups can be pushed across different levels of hierarchy by creating a Port Group. Commonly used interfaces can be captured as Net Groups and Port Groups. Examples of Net Groups include DDR3, PCI Express^® (PCIe^®), SATA, USB, and HDMI.

Port Groups can be created by attaching an IOPORT symbol to the Net Group. The Port Group is made available to higher-level blocks through the hierarchical block symbol where they appear with a new Pin Shape for unique identification.

Port Groups can be connected using a Net Group that has the same structure as a Port Group. The Port Group Mapping dialog box lets you view and edit the mapping between a Net Group and a Port Group.

Import of Pin Delay Properties in Front End

Pin Delay properties on the pins are required for correct calculation of the delay values between different pin pairs. When the pin pairs are defined in Constraint Manager connected to Allegro DE-HDL, only the Pin Delay values defined in the library are available. If the Pin Delay values were not defined in the library, they have to be imported in Allegro PCB Editor and then back annotated in Allegro DE-HDL Constraint Manager by running the back-to-front flow, which can become a tedious task.

A new Allegro DE-HDL console command is now provided to import a file containing the Pin Delay values, which can be used to define the complete delay for pin pairs. The format of this file is exactly the same as the one used for import/export by the Allegro PCB Editor.

Support for Page-Level Team Design with Allegro Design Authoring Team Design Option

A significant advancement in the design management features—now available with the Allegro 17.2-2016 release—is the ability to manage designs at the page level. What’s more, this is supported for both hierarchical and flat designs. Multiple team members can be assigned at a page level, using the team assignment “Pages” option. Any team member that is part of the page-level editing team can check out and edit a single page. This ability allows multiple engineers to edit different pages of the design at the same time. This feature has also been extended to work with constraints—any team member on the constraints team can check out and edit the constraints they have been assigned to.

What’s New in Allegro Capture

Graphical Design Difference Viewer

The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in Allegro Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis, between two schematics or two designs. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.

Advanced Annotation

With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property blocks giving them complete control over their component annotation process in the design cycle.

What’s New in Allegro AMS Simulator

PSpice Virtual Prototyping

This new functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++, SystemC—assisting them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

What’s New in Allegro FPGA System Planner

New Pin Assignment Options when Using the FPGA System Planner Engine in Allegro PCB Editor

• Swap two bundles: A new bundle swap option is now available in FPGA System Planner. If the two bundles are the same size, the PCB designer can select the bundles and ask the FPGA System Planner engine to swap them, pin for pin. A swap is useful when unforeseen circumstances cause bundles to cross over each other, as they might, for example, if a part has to be rotated 180 degrees in Allegro PCB Editor and the user could not have predicted this. To accomplish a bundle swap prior to the Allegro 17.2-2016 release, the PCB designer would either have to do multiple signal reassignments (assuming enough pins were even available on the FPGA or connector to be able to do this) or they would have to swap two pins at a time (which may also have limitations if there are constraints on the entire signal group, like a requirement that all signals go to the same bank).
  

  
  This bundle swap capability works not only with FPGAs but also with connectors.

  

  The caveat with swapping pins across connectors is that the connectors must be modeled as single-pin components in the schematic. Since the FPGA System Planner cannot generate single-pin components, the symbols for the connectors must come from the corporate library and used as-is when the design is captured.

• Three new manual pin-swap mode options: In addition to the new bundle-swap option, FPGA System Planner 17.2-2016 also offers three new manual pin-swapping algorithms: show all destination pins, show all destination pins in the same bank, and two-pin selection.
  
  • Show all destination pins highlights all valid destination pins across all connectors that can accept the signal(s).
    
  • Show all destination pins on component highlights all valid destination pins that can accept the signal but only within the same component. This algorithm is the only mode that was available prior to the Allegro 17.2-2016 release.

    

  • Show all destination pins in bank narrows the search to focus the FPGA System Planner engine, thereby delivering faster results: Two-pin selection allows the PCB designer to select two pins. If the selections are valid, the FPGA System Planner engine will swap the signals or move the signal to the new pin. If the selections are invalid, the FPGA System Planner engine will do nothing. This algorithm is useful when the PCB designer knows the FPGA well or has been given a large degree of freedom with regards to FPGA pin swapping.

Create Custom Connectors with User-Defined Groups and Pin Types

• Improved, robust connector modeling mechanism: Users can now create complex connector models with user-defined pin types and signal group capabilities. Models for parts that target the custom connector are created just like any other type of model, by defining the target family, the group constraint, and the target pin function.

Optimize Multiple, Separate FPGA System Planner Designs in Allegro PCB Editor

• Multiple FPGA System Planner designs feeding a single PCB design can now be optimized using the FPGA System Planner engine: When selecting the FPGA System Planner project in Allegro PCB Editor, the PCB designer can select any one of several projects that are part of the master design. The beauty of this enhancement is that not only does the Allegro use model remain unchanged from the Allegro 16.6 release, if the designs are structured to match any PCB concurrent design partitions, multiple PCB designers can use the FPGA System Planner engine and work on different designs at the same time.

Other Enhancements

• New “Targeted Pin View” option in the Design Connectivity window: Prior to the Allegro 17.2-2016 release, there were only two main ways to control what was displayed in the Design Connectivity Window: Net View, which displays every signal pin that could potentially be connected, and Pin View, which displays every pin for every instance. Now, a new “Targeted Pin View” is offered, which shows every pin of every interface and protocol specifically targeted to a device or connector. This view allows the user to focus on only those pins that they have intentionally targeted to a device.
• Enhanced net name template: This enhancement will be considered especially valuable by customers who have strict net naming requirements, since it allows users to define a common set of net naming templates that are automatically applied during schematic generation, which guarantees design consistency. There are two pieces to this enhancement: a more robust list of standard patterns to choose from, and the ability to define patterns in a CSV file.
• Instance-level targeted pin function override: This new feature allows a user to create a single model for connection to different types of FPGAs or connectors and then to select a Target Pin Function for a specific FPGA or connector at the instance level in the Design Connectivity Window.

• Hyperlinked error messages when checking protocols, rules, and virtual interfaces: The FPGA System Planner model/protocol/VI editor will faithfully report any errors. In previous releases, it reported these errors in a simple dump in the log window of the editor, making it difficult to determine exactly which entry was causing a given error message. With the Allegro 17.2-2016 release, when errors are reported, hyperlinked messages between the log window and the model itself make it easier to correlate a message to a specific pin on the model.