With the Cadence® Allegro® 17.2-2016 release, users can now embed a watermark in the generated PDF file. A watermark can either be text or an image placed as a background on all the pages of the PDF file. For example, text such as “First Prototype”, “Confidential”, or “Review Copy” can be added as a watermark. Similarly, the company’s logo is an example of an image as a watermark. Using a watermark on the generated schematic PDF file is optional. You have the option to use it only while viewing the PDF file, only when printing the file, for both viewing and printing, or not at all.
ECSet nodes now support tags (pin parameter) that can be used to uniquely identify a pin and remove any ambiguity. They can be used to lock the mapping between the ECSet and associated nets, and will not be impacted by the placement or the RefDes changes.
Tags can be defined in a design prior to ECSet extraction or ECSet application in Constraint Manager, and can also be defined in SigXplorer. Tags can be added to pins in a design prior to extracting a topology into SigXplorer. The tags can be used to schedule a topology and to apply the topology back to the design.
Nets that have similar functionality can be grouped together to create a Net Group. Net Groups help in managing the nets as a single object and provide a higher level of abstraction for the design purposes. Net Groups can be pushed across different levels of hierarchy by creating a Port Group. Commonly used interfaces can be captured as Net Groups and Port Groups. Examples of Net Groups include DDR3, PCI Express® (PCIe®), SATA, USB, and HDMI.
Port Groups can be created by attaching an IOPORT symbol to the Net Group. The Port Group is made available to higher-level blocks through the hierarchical block symbol where they appear with a new Pin Shape for unique identification.
Port Groups can be connected using a Net Group that has the same structure as a Port Group. The Port Group Mapping dialog box lets you view and edit the mapping between a Net Group and a Port Group.
Pin Delay properties on the pins are required for correct calculation of the delay values between different pin pairs. When the pin pairs are defined in Constraint Manager connected to Allegro DE-HDL, only the Pin Delay values defined in the library are available. If the Pin Delay values were not defined in the library, they have to be imported in Allegro PCB Editor and then back annotated in Allegro DE-HDL Constraint Manager by running the back-to-front flow, which can become a tedious task.
A new Allegro DE-HDL console command is now provided to import a file containing the Pin Delay values, which can be used to define the complete delay for pin pairs. The format of this file is exactly the same as the one used for import/export by the Allegro PCB Editor.
A significant advancement in the design management features—now available with the Allegro 17.2-2016 release—is the ability to manage designs at the page level. What’s more, this is supported for both hierarchical and flat designs. Multiple team members can be assigned at a page level, using the team assignment “Pages” option. Any team member that is part of the page-level editing team can check out and edit a single page. This ability allows multiple engineers to edit different pages of the design at the same time. This feature has also been extended to work with constraints—any team member on the constraints team can check out and edit the constraints they have been assigned to.
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in Allegro Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis, between two schematics or two designs. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property blocks giving them complete control over their component annotation process in the design cycle.
This new functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++, SystemC—assisting them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
This bundle swap capability works not only with FPGAs but also with connectors.
The caveat with swapping pins across connectors is that the connectors must be modeled as single-pin components in the schematic. Since the FPGA System Planner cannot generate single-pin components, the symbols for the connectors must come from the corporate library and used as-is when the design is captured.
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