Cadence® PHY IP for PCI Express® (PCIe®) 5.0 available in advanced FinFET technologies provides best-in-class power efficiency, enabling low-latency solutions for applications from storage, networking, artificial intelligence and machine learning (AI/ML), and high-performance computing (HPC). Cadence’s silicon-proven PAM4 designs with our storied PCIe experience are showcased in our PHY IP for PCIe 6.0, which supports the next revision of CXL. Networking applications are enabled through support for CEI-56G and 25G-KR. For PHY IP optimized for PCIe 3.0 and PCIe 4.0, visit Cadence PHYs for PCIe.
Cadence PHY IP for PCIe and CXL is designed to provide best-in-class power efficiency for the latest PCIe standards while meeting data and clock recovery requirements in high-speed, high-dB-loss, and high-crosstalk channels
The PHY IP is easily configurable to meet application needs for multi-link use cases, support for Ethernet and PCIe protocols makes it versatile for most common applications in the HPC space
Designed for the future
The PHY IP is available in advanced FinFET process nodes and designed for the most challenging low-latency applications made possible by newer versions of the PCIe and CXL standards.