64GTps PHY IP for PCIe 6.0 for TSMC 5nm FinFET
Designed specifically for infrastructure and data center applications
Cadence PHY IP for PCIe is designed for advanced FinFET technologies, providing best-in-class power efficiency for low-latency solutions for storage, networking, AI/ML, and HPC applications using PCI Express® (PCIe®) 6.0 and 5.0, Compute Express Link (CXL), and Ethernet.
Increased data bandwidth per lane at improved power efficiency
Solutions for lowest active and standby power with lowest exit latency
Scalable multi-protocol solutions with lowest active power, security, and remote access service (RAS) features