Cadence PHY IP for PCIe is designed for advanced FinFET technologies, providing best-in-class power efficiency for low-latency solutions for storage, networking, AI/ML, and HPC applications using PCI Express® (PCIe®) 6.0 and 5.0, Compute Express Link (CXL), and Ethernet.

Key Benefits


  • Cadence PHY IP for PCIe and CXL is designed to provide the best-in-class power efficiency for the latest PCIe standards while meeting data and clock recovery requirements in high-speed, high-dB-loss, high-crosstalk channels
  • Support for latest power-saving engineering change notices (ECNs).


  • The PHY IP is easily configurable to meet application needs for multi-link use cases. 
  • Support for Ethernet and PCIe protocols makes it versatile for most common applications in the high-performance computing space
  • Controller IP configurable for application-specific needs

Designed for the Future

  • PHY IP available in advanced FinFET process nodes
  • Controller IP supports PCIe 6.0 and 5.0 and CXL with low latency



Increased data bandwidth per lane at improved power efficiency

Storage and Persistent Memory

Solutions for lowest active and standby power with lowest exit latency

Enterprise, Cloud, and Data Center Solutions

Scalable multi-protocol solutions with lowest active power, security, and remote access service (RAS) features