Overview

With growing demand for flash memory in automotive, IoT, and consumer applications, the Cadence® Host Controller IP for xSPI offers up to eight flash Serial Peripheral Interfaces (i.e., Octal SPI, HyperFlash, xSPI) to further increase the Serial Flash Memory throughput while providing backwards compatibility with single, dual, and quad SPI interfaces.

usb2-controller

Key Benefits

Flexibility

Multiple SPI protocol support within single IP

Simplicity

PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing

High Performance

Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)

Features

Supports JEDEC SFDP
  • Serial Function Discoverable Parameters allow boot from unknown devices
All-Digital Storage Combo PHY IP
  • Accurate data sampling training, eliminates the need for high-speed clock for SPI interface
Memory Mapped
  • Enables either boot or XIP functionality
  • Support for Multi-CMD Channels